Semiconductor device having metal gate electrode and method of fabrication thereof

Patent metadata

Field	Value
Publication number	US-9337110-B2
Application number	US-201113276859-A
Country	US
Kind code	B2
Filing date	Oct 19, 2011
Priority date	Oct 19, 2011
Publication date	May 10, 2016
Grant date	May 10, 2016

Abstract

The present disclosure provides a method including providing a substrate having a first opening and a second opening on the substrate. A blocking layer is formed in the first opening. A second metal gate electrode is formed the second opening while the blocking layer is in the first opening. The blocking layer is then removed from the first opening, and a first metal gate electrode formed. In embodiments, this provides for a device having a second gate electrode that includes a second work function layer and not a first work function layer, and the first gate electrode includes the first work function layer and not the second work function layer.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, comprising:
providing a substrate having a first region and a second region, wherein the first region includes a first opening and the second region includes a second opening;
filling the second opening with a blocking material, wherein the blocking material comprises at least one of amorphous silicon, spin on glass, silicon dioxide, and silicon nitride (Si 3 N 4 );
forming a first gate electrode in the first opening while the blocking material fills the second opening, wherein the forming the first gate electrode in the first opening, includes:
forming a first work function layer directly on a gate dielectric layer;
forming a first fill metal layer directly on the first work function layer; and
planarizing the first fill metal layer such that its top surface is coplanar with a top surface of the blocking material in the second opening;

removing the blocking material after forming the first gate electrode; and
forming a second gate electrode in the second opening, wherein the second gate electrode includes a second work function layer and not the first work function layer, and the first gate electrode includes the first work function layer and not the second work function layer, and wherein the forming the second gate electrode in the second opening, includes:
forming the second work function layer directly on the gate dielectric layer; and
forming a second fill metal layer directly on the second work function layer.

2. The method of claim 1 , further comprising:
forming a first dummy gate structure in the first region and a second dummy gate structure in the second region of the substrate; and
removing the first and second dummy gate structures to form the first opening and the second opening, wherein the first and second openings are formed in a layer disposed on the substrate.

3. The method of claim 1 , wherein the first work function layer is an n-type work function layer and the second work function layer is a p-type work function layer.

4. The method of claim 1 , wherein the forming the first gate electrode includes forming the first work function layer having a material selected from the group consisting of Ti, Ag, Al, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, and Zr.

5. The method of claim 4 , wherein the forming the second gate electrode includes forming the second work function layer having a material selected from the group consisting of: TiN, TaN, Ru, Mo, WN, ZrSi 2 , MoSi 2 , TaSi 2 , NiSi 2 , and WN.

6. The method of claim 1 , wherein the first and second fill metal layers have the same composition.

7. A method comprising:
forming a first opening and a second opening on a substrate;
depositing a blocking layer in the first opening, wherein the blocking material is selected from the group consisting of spin on glass, silicon dioxide, and silicon nitride (Si 3 N 4 );
planarizing the blocking layer such that its top surface of the selected one of spin on glass, silicon dioxide, and silicon nitride (Si 3 N 4 ) is coplanar with a top of the first opening;
after planarization, forming a second metal gate electrode in the second opening while the blocking layer is in the first opening;
removing the blocking layer from the first opening after forming the second metal gate electrode; and
forming a first metal gate electrode in the first opening after removing the blocking layer.

8. The method of claim 7 , wherein the forming the first opening and the second opening includes:
forming a first dummy gate structure and a second dummy gate structure;
forming a dielectric layer interposing the first and second dummy gate structures;
removing the first dummy gate structure to form the first opening; and
removing the second dummy gate structure to form the second opening.

9. The method of claim 7 , wherein the forming the blocking layer in the first opening includes depositing silicon nitride (Si 3 N 4 ).

10. The method of claim 7 , further comprising:
forming the blocking layer in the second opening concurrently with forming the blocking layer in the first opening;
forming a masking element on the blocking layer in the first opening; and
removing the blocking layer in the second opening while the masking element is disposed on the blocking layer in the first opening.

11. The method of claim 7 , wherein the forming the second metal gate electrode includes forming an n-type work function layer and a fill layer.

12. The method of claim 11 , wherein the forming the first metal gate electrode includes forming a p-type work function layer.

13. The method of claim 7 , wherein the forming the second metal gate electrode includes forming an n-type work function layer and not a p-type work function layer, and forming a fill layer overlying the n-type work function layer.

14. The method of claim 13 , wherein the forming the first metal gate electrode includes forming a p-type work function layer and not an n-type work function layer.

15. The method of claim 1 , wherein the blocking layer includes silicon oxide in the first opening.

16. The method of claim 1 , wherein the blocking layer includes spin on glass (SOG) layer in the first opening.

17. The method of claim 1 , wherein the removing the blocking material includes applying a solution including at least one of NH 4 OH, dilute-HF (DHF), a solvent, or phosphoric acid.

Assignees

• Lee Da-Yuan
• Hsu Kuang-Yuan
• Taiwan Semiconductor Mfg

Inventors

• Lee Da-Yuan
• Hsu Kuang-Yuan

Classifications

• H10D64/017 Primary

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D84/0177 Primary

  the gate conductors having different materials or different implants · CPC title

• H10D64/685

  being perpendicular to the channel plane · CPC title

• H10D64/691

  comprising metallic compounds, e.g. metal oxides or metal silicates  (insulators comprising nitrogen H10D64/693) · CPC title

• H10D64/668

  the layer being a silicide, e.g. TiSi2 · CPC title