Method for manufacturing semiconductor device including doping epitaxial source drain extension regions

Patent metadata

Field	Value
Publication number	US-9337102-B2
Application number	US-201514725496-A
Country	US
Kind code	B2
Filing date	May 29, 2015
Priority date	Sep 11, 2014
Publication date	May 10, 2016
Grant date	May 10, 2016

Abstract

A method for manufacturing a semiconductor device comprises, including forming a plurality of fins on a substrate, forming, a dummy gate stack on the fins forming a gate spacer on opposite sides of the dummy gate stack, forming source/drain trenches by etching the fins with the gate spacer and the dummy gate stack as a mask, forming source/drain extension regions on the bottom and sides of the trenches by performing lightly-doping ion implantation; and by performing epitaxial growth in and/or on the source/drain trenches, removing the dummy gate stack to form a gate trench; and forming a gate stack in the gate trench.

First claim

We claim:

1. A method for manufacturing a semiconductor device, comprising:
forming, on a substrate, a plurality of fins extending along a first direction;
forming, on the fins, a dummy gate stack extending along a second direction;
forming a gate spacer on opposite sides of the dummy gate stack in the first direction;
etching the fins with the gate spacer and the dummy gate stack as a mask, to form source/drain trenches;
performing lightly-doping ion implantation to form source/drain extension regions on bottom and side walls of the source/drain trenches;
performing epitaxial growth in and/or on the source/drain trenches to form source/drain regions;
removing the dummy gate stack to form a gate trench; and
forming a gate stack in the gate trench.

2. The method according to claim 1 , wherein before forming the dummy gate stack, the method further comprises performing ion implantation to form a punch-through stop layer in the middle and/or at the bottom of the fins.

3. The method according to claim 2 , wherein the source/drain trenches each have a bottom above the punch-through stop layer, with a part of fins remaining therebetween.

4. The method according to claim 1 , wherein the source/drain extension regions each have a thickness of 5-30 nm.

5. The method according to claim 1 , wherein the source/drain trenches are formed by anisotropic etching to have vertical side walls.

6. The method according to claim 5 , wherein after the source/drain trenches having the vertical side walls are formed, recesses are formed in the side walls of the source/drain trenches by isotropic etching.

7. The method according to claim 1 , wherein in performing the lightly-doping ion implantation, a vertical tilt angle and/or horizontal tilt angle is adjusted to control a junction depth of the source/drain extension regions in a vertical direction and/or the first direction.

8. The method according to claim 1 , wherein before forming the gate trench, the method further comprises:
epitaxially growing raised source/drain regions on the source/drain regions;
forming a second gate spacer on the gate spacer;
performing heavily-doping ion implantation with the second gate spacer as a mask, to adjust a doping type and/or a doping concentration of the raised source/drain regions; and
performing annealing to activate doped ions and/or repairing damages due to the ion implantation.

9. The method according to claim 8 , wherein after performing annealing, the method further comprises forming a contact etching stop layer and an inter-layer dielectric layer on the device.

10. The method according to claim 1 , wherein the gate stack comprises a gate insulating layer of a high-K material and a gate conductive layer of a metal material.

Assignees

• Inst Of Microelectroics Chinese Academy Of Sciences
• Inst Of Microelectronics Cas

Inventors

• Yin Huaxiang
• Qin Changliang
• Ma Xiaolong
• Wang Guilei
• Zhu Huilong

Classifications

• H10P30/209

  in silicon to make buried insulating layers · CPC title

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P30/222

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/22

  using masks · CPC title