Package for three dimensional integrated circuit

Patent metadata

Field	Value
Publication number	US-9337063-B2
Application number	US-201414323960-A
Country	US
Kind code	B2
Filing date	Jul 3, 2014
Priority date	Nov 16, 2011
Publication date	May 10, 2016
Grant date	May 10, 2016

Abstract

A wafer level package includes a semiconductor die bonded on a supporting wafer. The semiconductor die has at least a step recess at its substrate. An underfill layer is formed between the semiconductor die and the supporting wafer. Moreover, the height of the underfill layer is limited by the step recess. During a fabrication process of the wafer level package, the step recess helps to reduce the stress on the wafer level package.

First claim

What is claimed is:

1. A method comprising:
applying a first dicing process to a wafer comprising a plurality of semiconductor dies, wherein a thick blade is employed to partially cut through the wafer and a step recess is formed at a first side of a semiconductor die;
applying a second dicing process to the wafer, wherein a thin blade is employed to cut through the wafer to separate the plurality of semiconductor dies from the wafer;
attaching the first side of the semiconductor die on a first side of a package substrate; and
forming an underfill layer between the semiconductor die and the package substrate, wherein the underfill layer is below the step recess.

2. The method of claim 1 , further comprising:
applying the first dicing process to the wafer using the thick blade having a thickness in a range from about 40 um to about 400 um.

3. The method of claim 1 , further comprising:
dispensing an underfill material into a gap between the semiconductor die and the package substrate; and
applying a curing process to the underfill material.

4. The method of claim 3 , wherein:
the underfill material is epoxy.

5. The method of claim 1 , further comprising:
depositing a molding compound layer over the semiconductor die and the package substrate, wherein the semiconductor die is embedded in the molding compound layer.

6. The method of claim 5 , further comprising:
applying a thinning process to a backside of the semiconductor die, wherein after the step of applying the thinning process to the backside of the semiconductor die, the backside of the semiconductor die is level with a top surface of the molding compound layer.

7. A method comprising:
cutting into a semiconductor die with a first dicing depth using a first dicing saw;
cutting through the semiconductor die with a second dicing saw to separate the semiconductor die from a wafer, wherein the second dicing saw has a second blade different from a first blade of the first dicing sawing;
forming a step recess at one side of the semiconductor die;
flipping the semiconductor die;
attaching a first side of the semiconductor die on a first side of a package substrate; and
forming an underfill layer between the semiconductor die and the package substrate, wherein the underfill layer is below the step recess.

8. The method of claim 7 , further comprising:
forming a compound layer on the package substrate, wherein the semiconductor die is embedded in the compound layer.

9. The method of claim 8 , further comprising:
removing an upper portion of the compound layer until a second side of the semiconductor die becomes exposed; and
thinning the second side of the semiconductor die.

10. The method of claim 7 , further comprising:
thinning a second side of the package substrate until a plurality of vias become exposed.

11. The method of claim 10 , further comprising:
forming an isolation layer on the second side of the package substrate;
forming a redistribution layer on the second side of the package substrate;
forming a under bump metal structure on the redistribution layer; and
forming a bump on the under bump metal structure.

12. A method comprising:
partially cutting through a wafer using a first dicing process, wherein the wafer comprises a plurality of semiconductor dies, wherein each semiconductor die is enclosed by four trenches;
cutting through the wafer to separate the plurality of semiconductor dies from the wafer using a second dicing process;
attaching a first side of a semiconductor die on a first side of a package substrate;
thinning a second side of the package substrate until a plurality of vias of the package substrate become exposed; and
forming a bump on the second side of the package substrate, wherein the bump is electrically coupled to at least one via.

13. The method of claim 12 , further comprising:
partially cutting through the wafer using a first blade and cutting through the wafer using a second blade, wherein a thickness of the first blade is greater than a thickness of the second blade.

14. The method of claim 13 , further comprising:
applying the second dicing process to the trenches, wherein a trench is cut through by the second blade along a middle line of the trench.

15. The method of claim 13 , further comprising:
applying the second dicing process to the trenches, wherein a trench is cut through by the second blade along a sidewall of the trench.

16. The method of claim 13 , wherein:
a sidewall of the trench is substantially straight.

17. The method of claim 13 , wherein:
a sidewall of the trench is of a slope shape.

18. The method of claim 13 , wherein:
a sidewall of the trench is of a curved shape.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Chen Chih-Hao
• Lee Long Hua
• Su Chun-Hsing
• Tsai Yi-Lin
• Yeh Kung-Chen
• Wang Chung Yu
• Hung Jui-Pin
• Lin Jing-Cheng

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W72/0198

  batch processes · CPC title