Multiple phase change materials in an integrated circuit for system on a chip application

Patent metadata

Field	Value
Publication number	US-9336879-B2
Application number	US-201514603647-A
Country	US
Kind code	B2
Filing date	Jan 23, 2015
Priority date	Jan 24, 2014
Publication date	May 10, 2016
Grant date	May 10, 2016

Abstract

A device includes first and second pluralities of memory cells with memory elements and first and second capping materials on the first and second pluralities of memory cells. First and second capping materials can comprise lower and higher density silicon nitrides. The memory elements can include a programmable resistance memory material, and the capping materials can contact the memory elements. The first and second pluralities of memory cells can have a common cell structure. The first memory cells in the can comprise a top and bottom electrodes with a memory material therebetween and the first capping material contacting the memory material. Control circuits can apply different write algorithms to the first and second pluralities of memory cells. The first and second sets of memory cells can have different operational memory characteristics by forming the first and second capping layers using different capping materials but with the same cell structure.

First claim

What is claimed is:

1. A system-on-chip memory device, comprising:
a first plurality of memory cells comprising memory elements and a first capping material on the first plurality of memory cells;
a second plurality of memory cells comprising the memory elements and a second capping material on the second plurality of memory cells;
the first capping material being different from the second capping material and cell structures of the first plurality of memory cells and the second plurality of memory cells are same;
wherein the first capping material comprising a silicon nitride, the second capping material comprising a silicon nitride having a higher density than the silicon nitride of the first capping material; and
circuitry configured to apply a write algorithm to the first plurality of memory cells and a different write algorithm to the second plurality of memory cells to have different operational characteristics.

2. The device according to claim 1 , wherein the memory elements comprising a programmable resistance memory material, and the first capping material and the second capping material contact the memory elements of the corresponding first and second pluralities of memory cells.

3. The device according to claim 1 , wherein the memory elements comprising a GexSbyTez phase change material; and the second capping material deposited at a higher temperature than that of the first capping material.

4. The device according to claim 1 , wherein the first capping material comprises a material with refractive index of less than 2.016 and greater than 1.8.

5. The device according to claim 1 , wherein the first capping material comprises a material with density of less than 3.2 g/cm 3 and greater than 2.4 g/cm 3 .

6. The device according to claim 1 , the memory elements comprising a phase change material.

7. The device according to claim 1 , wherein the memory cells of the first plurality of memory cells comprises a top electrode, a bottom electrode, and the memory elements, the memory elements being between the top and bottom electrodes, the first capping material contacting the memory elements.

8. A system-on-chip memory device, comprising:
a first plurality of memory cells having a cell structure with memory elements comprising phase change material, and a first capping layer of silicon nitride contacting the memory elements in the first plurality of memory cells;
a second plurality of memory cells having a cell structure with memory elements comprising phase change material, and a second capping layer of silicon nitride contacting the memory elements in the second plurality of memory cells, the cell structures of the first and second pluralities of memory cells differing only in the materials of the first and second capping layers; the silicon nitride in the first capping layer having a lower density than the silicon nitride in the second capping layer; and
circuitry configured to apply a higher speed write operation to the first plurality of memory cells than to the second plurality of memory cells to have different operational characteristics.

Assignees

• Macronix Int Co Ltd

Inventors

• Lung Hsiang-Lan
• Wu Chao-I
• Chien Wei-Chih

Classifications

• G11C13/0069 Primary

  Writing or programming circuits or methods · CPC title

• G11C13/0064

  Verifying circuits or methods · CPC title

• G11C13/0004

  comprising amorphous/crystalline phase transition cells · CPC title

• H01L45/144

  Electricity · mapped topic

• H01L45/06

  Electricity · mapped topic