Method of producing multilayer circuit board

Patent metadata

Field	Value
Publication number	US-9332650-B2
Application number	US-201213494417-A
Country	US
Kind code	B2
Filing date	Jun 12, 2012
Priority date	Apr 30, 2008
Publication date	May 3, 2016
Grant date	May 3, 2016

Abstract

The present invention relates to a method of producing a multilayer circuit board including: a film-forming step of forming a swellable resin film on the surface of an insulative substrate, a circuit groove-forming step of forming circuit grooves having a depth equal to or greater than the thickness of the swellable resin film on the external surface of the film, a catalyst-depositing step of depositing a plating catalyst or the precursor thereof on the surface of the circuit grooves and the surface of the swellable resin film, a film-separating step of swelling the swellable resin film with a particular liquid and then separating the swollen resin film from the insulative substrate surface, and a plating processing step of forming an electrolessly plated film only in the region where the plating catalyst or the plating catalyst formed from the plating catalyst precursor remains unseparated after separation of the film.

First claim

What is claimed is:

1. A method of producing a multilayer circuit board, comprising:
forming a resin film having an external surface on the surface of an insulation layer formed on a circuit board that embeds a conductive rod protruding at predetermined positions of a first electrical circuit;
forming circuit grooves having a depth equal to or greater than the thickness of the resin film by laser processing on the external surface of the resin film;

exposing the conductive rod by laser processing from the external surface of the resin film;
depositing a plating catalyst or the precursor thereof on the surface of the exposed conductive rod, circuit grooves in the insulation layer, the internal wall of the pores formed in the insulation layer by exposure of the conductive rod, and the surface of the resin film;
removing the resin film; and
forming a second electrical circuit by forming an electrolessly plated film in the region where the plating catalyst remains unremoved after the removing the resin film and connecting the first and the second electrical circuits to each other with the conductive rod by interlayer connection.

2. The method of producing a multilayer circuit board according to claim 1 , wherein the circuit board carrying the embedded conductive rod has a conductive film for heat radiation containing a conductive rod formed as electrically insulated from the first electrical circuit additionally on the surface having the first electrical circuit formed; and the conductive rod in the conductive film for heat radiation is embedded in the insulation layer together with the conductive rod protruding in the first electrical circuit; the exposing the conductive rod includes exposing the conductive rod formed protruding in the conductive film for heat radiation by laser processing from the external surface of the resin film; wherein, in the depositing a plating catalyst or the precursor thereof, a plating catalyst or the precursor thereof is deposited additionally on the surface of the conductive rod exposed in the conductive film for heat radiation and the internal wall of the hole formed in the insulative layer by exposure of the conductive rod; and the a secondary radiator connected to the a first radiator by interlayer connection is formed in the forming a second electrical circuit.

3. The method of producing a multilayer circuit board according to claim 1 , wherein the laser processing for exposure of the conductive rod removes part of the top region of the conductive rod.

4. The method of producing a multilayer circuit board according to claim 1 , wherein the resin film contains a fluorescent substance, and the method includes examining film-removing failure by monitoring emission from the fluorescent substance after the removing the resin film.

5. The method of producing a multilayer circuit board according to claim 1 , wherein the resin film is a swellable resin film separated from the insulation layer surface as it is swollen with a particular liquid.

6. The method of producing a multilayer circuit board according to claim 1 , wherein the circuit board that embeds a conductive rod is a substrate obtained by laminating an insulation layer integrally on the surface having a conductive rod previously formed as it protrudes at a predetermined position in the first electrical circuit.

7. The method of producing a multilayer circuit board according to claim 1 , wherein the circuit board that embeds a conductive rod is a substrate obtained by coating a resin solution on the surface having a conductive rod previously formed as it protrudes at a predetermined position in the first electrical circuit and hardening it into an insulation layer.

8. The method of producing a multilayer circuit board according to claim 1 , wherein the circuit board that embeds a conductive rod is a substrate obtained by forming an insulation layer on the surface of the first electrical circuit, exposing the first electrical circuit by laser processing from the surface of the insulation layer, and forming a conductive rod on the surface of the first electrical circuit by growing a plated film from the exposed first electrical circuit.

9. The method of producing a multilayer circuit board according to claim 8 , wherein the growing a plated film comprises growing a plated film by electrolytic plating by using the first electrical circuit exposed after desmear treatment of the laser-processed region as electrode.

10. The method of producing a multilayer circuit board according to claim 8 , wherein the growing a plated film comprises growing a plated film by electroless plating by using the first electrical circuit exposed after desmear treatment of the laser-processed region as plating nucleus.

Assignees

• Yoshioka Shingo
• Fujiwara Hiroaki
• Panasonic Corp

Inventors

• Yoshioka Shingo
• Fujiwara Hiroaki

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W70/655

  Fan-out layouts · CPC title

• H05K2203/0565

  Resist used only for applying catalyst, not for plating itself · CPC title

• H05K2203/0108

  Male die used for patterning, punching or transferring · CPC title

• H05K2201/09736

  Varying thickness of a single conductor; Conductors in the same plane having different thicknesses · CPC title