Methods and circuits for reverse battery protection

Patent metadata

Field	Value
Publication number	US-9331478-B2
Application number	US-201414222925-A
Country	US
Kind code	B2
Filing date	Mar 24, 2014
Priority date	Mar 24, 2014
Publication date	May 3, 2016
Grant date	May 3, 2016

Abstract

A circuit is configured for providing reverse battery protection. The circuit includes a load driver circuit having at least a first half-bridge circuit with topside and bottomside transistors coupled at a midpoint node by a first current terminal of both the topside and bottomside transistors. A second current terminal of the bottomside transistor is coupled to a voltage common node. The circuit also includes: a reverse battery protection transistor having a first current terminal coupled to a battery supply node and a second current terminal coupled to a second current terminal of the topside transistor; a bootstrap capacitor having a first terminal coupled to a the midpoint node between the topside and bottomside transistors of the first half-bridge circuit; and a diode having an anode coupled to a second terminal of the bootstrap capacitor and a cathode coupled to a control terminal of the reverse battery protection transistor.

First claim

What is claimed is:

1. A circuit configured for providing reverse battery protection, the circuit comprising:
a load driver circuit comprising at least a first half-bridge circuit, with each half-bridge circuit having a topside transistor and a bottomside transistor coupled at a corresponding midpoint node by a first current terminal of both the topside and bottomside transistors, wherein a second current terminal of each bottomside transistor is coupled to a voltage common node;
a reverse battery protection transistor having a first current terminal coupled to a battery supply node and a second current terminal coupled to a second current terminal of each topside transistor;
a first capacitor having a first terminal coupled to a first midpoint node between first topside and bottomside transistors of the first half-bridge circuit;
a first diode having an anode coupled to a second terminal of the first capacitor and a cathode coupled to a control terminal of the reverse battery protection transistor.

2. The circuit of claim 1 , wherein the reverse battery protection transistor is an N-channel metal-oxide semiconductor field-effect transistor.

3. The circuit of claim 2 further comprising a turn-off circuit that includes a turn-off transistor having a first current terminal coupled to the battery supply node, a second current terminal coupled to the control terminal of the reverse battery protection transistor, and a control terminal coupled between the battery supply node and the voltage common node.

4. The circuit of claim 3 , wherein the turn-off transistor is an NPN bipolar junction transistor.

5. The circuit of claim 2 , wherein the topside and bottomside transistors of each half-bridge circuit are N-channel metal-oxide semiconductor field-effect transistors.

6. The circuit of claim 1 , wherein the load driver circuit is an H-bridge circuit comprising the first half-bridge circuit and a second half-bridge circuit having second topside and bottomside transistors coupled at a second midpoint node, wherein the circuit further comprises a second capacitor having first and second terminals, wherein the first terminal is coupled to the second midpoint node.

7. The circuit of claim 6 further comprising:
a second diode having an anode coupled to the second terminal of the second capacitor and a cathode coupled to the control terminal of the reverse battery protection transistor.

8. The circuit of claim 1 , wherein the load driver circuit is a three phase inverter circuit comprising the first half-bridge circuit, a second half-bridge circuit having second topside and bottomside transistors coupled at a second midpoint node, and a third half-bridge circuit having third topside and bottomside transistors coupled at a third midpoint node, wherein the circuit further comprises:
a second capacitor having first and second terminals, wherein the first terminal of the second capacitor is coupled to the second midpoint node;
a third capacitor having first and second terminals, wherein the first terminal of the third capacitor is coupled to the third midpoint node.

9. The circuit of claim 8 further comprising at least one of:
a second diode having an anode coupled to the second terminal of the second capacitor and a cathode coupled to the control terminal of the reverse battery protection transistor; or
a third diode having an anode coupled to the second terminal of the third capacitor and a cathode coupled to the control terminal of the reverse battery protection transistor.

10. The circuit of claim 1 further comprising a control circuit coupled between the first capacitor and a control terminal of each topside transistor of the load driver circuit, wherein:
the first capacitor is configured to provide a transistor enhancement voltage level through the first diode to the control terminal of the reverse battery protection transistor during a forward battery condition across the battery supply node and the voltage common node; and
the control circuit is configured to route the transistor enhancement voltage level to a control terminal of at least one of the topside transistors during the forward battery condition, wherein the transistor enhancement voltage level is configured to cause the reverse battery protection transistor and the at least one topside transistor to operate in enhancement mode during the forward battery condition.

11. A method performed in a circuit configured for providing reverse battery protection, the method comprising:
generating a first voltage level at a second terminal of a first capacitor, wherein a first terminal of the first capacitor is coupled to a load driver circuit at a first midpoint node between first topside and bottomside transistors of the load driver circuit, wherein the first voltage level is generated while the first bottomside transistor is on and the first topside transistor is off;
boosting the voltage level at the second terminal of the first capacitor to a second voltage level that is higher than the first voltage level while the first bottomside transistor is off and the first topside transistor is on;
providing the second voltage level to a control terminal of a reverse battery protection transistor that is coupled in series with the load driver circuit between a battery supply node and a voltage common node, wherein the second voltage level is provided through a first diode coupled in series with the first capacitor between the first midpoint node and the control terminal of the reverse battery protection transistor.

12. The method of claim 11 , wherein the second voltage level maintains the reverse battery protection transistor in enhancement mode during a forward battery condition across the battery supply node and the voltage common node.

13. The method of claim 12 , wherein the reverse battery protection transistor blocks current through the load driver circuit during a reverse battery condition across the battery supply node and the voltage common node.

14. The method of claim 12 further comprising, at a start of the reverse battery condition, turning off the reverse battery protection transistor using a turn off transistor coupled to the control terminal of the reverse battery protection transistor.

15. The method of claim 12 further comprising routing the second voltage level to a control terminal of the first topside transistor to cause the first topside transistor to operate in an enhancement mode during the forward battery condition.

16. The method of claim 11 , wherein the load driver circuit comprises at least one other topside and bottomside transistor coupled to at least one other midpoint node, the method further comprising providing to the load driver circuit a pulse width modulation control signal to switch the topside transistors on and off at different times, wherein during a first pulse width modulation cycle when the first topside transistor is on, the first bottomside transistor is off and at least one other topside transistor is off, the second voltage level is provided to the control terminal of the reverse battery protection transistor through the first diode coupled in series with the first capacitor.

17. The method of claim 16 , wherein during a second pulse width modulation cycle when the first topside transistor is off, the first bottomside transistor is on, and at least one other topside transistor is on;
the first diode delays decay of the second voltage level at the control terminal of the reverse battery protection transistor such that the reverse battery protection transistor remains in an enhancemen

Assignees

• Reiter Thomas J
• Kandah Ibrahim S
• Freescale Semiconductor Inc

Inventors

• Reiter Thomas J
• Kandah Ibrahim S

Classifications

• H02H11/002 Primary

  in case of inverted polarity or connection; with switching for obtaining correct connection · CPC title