Method for improving device performance using epitaxially grown silicon carbon (SiC) or silicon-germanium (SiGe)

Patent metadata

Field	Value
Publication number	US-9331174-B2
Application number	US-76068810-A
Country	US
Kind code	B2
Filing date	Apr 15, 2010
Priority date	Apr 15, 2010
Publication date	May 3, 2016
Grant date	May 3, 2016

Abstract

A semiconductor substrate including a field effect transistor (FET) and a method of producing the same wherein a stressor is provided in a recess before the source/drain region is formed. The device has an increased carrier mobility in the channel region adjacent to the gate electrode.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a semiconductor substrate;
a transistor gate electrode at the surface of said semiconductor substrate;
a gate dielectric on said surface of the semiconductor substrate beneath the transistor gate electrode, said gate dielectric having a thickness from about 0.5 to about 20 nanometers;
an offset spacer abutting the transistor gate electrode at each end of the transistor gate;
a recess in said surface at said each end;
an epi layer of doped silicon germanium (SiGe) or silicon carbide (SiC), said epi layer epitaxially grown in, and filling, each said recess to said surface;
a source/drain spacer on an end of said epi layer at said surface abutting said offset spacer at said each end;
a source/drain extension under each said source/drain spacer, the portion of a respective said epi layer under said each source/drain spacer forming each said source/drain extension; and
a source/drain diffusion region formed in said epi layer and said recess at said each source/drain extension, wherein the source/drain spacers above said each source/drain extension delimit said source/drain regions.

2. The semiconductor structure according to claim 1 , wherein the epi layer is n-doped.

3. The semiconductor structure according to claim 1 , wherein the epi layer is p-doped.

4. The semiconductor structure according to claim 1 , wherein the epi layer has a thickness of from 5 to 30 nm.

5. The semiconductor structure according to claim 1 , wherein the epi layer has a thickness of from 5 to 15 nm.

6. The semiconductor structure according to claim 1 , wherein the epi layer is a SiC layer with a carbon content of from 0.5 to 5% by weight based on the weight of the SiC layer.

7. The semiconductor structure according to claim 1 , wherein the gate dielectric is an insulating material selected from an oxide, nitride, or oxynitride.

8. The semiconductor structure according to claim 1 , wherein the gate dielectric is nitride SiO 2 or oxynitride.

9. The semiconductor structure according to claim 1 , wherein the transistor gate electrode comprises doped silicon.

10. The semiconductor structure according to claim 1 , wherein the semiconductor substrate comprises silicon, SiGe, SiC, SiGeC, or a combination thereof.

11. The semiconductor structure according to claim 1 , wherein the semiconductor substrate is a silicon-on-silicon substrate.

12. A semiconductor structure comprising:
a semiconductor substrate;
a transistor gate electrode at the surface of said semiconductor substrate;
an offset spacer abutting the transistor gate electrode at each end of the transistor gate;
a recess in said surface at said each end;
an epi layer of doped silicon carbide (SiC) with a carbon content of from 0.5 to 5% by weight based on the weight of the epi layer, said epi layer epitaxially grown in, and filling, each said recess to said surface;
a source/drain spacer on an end of said epi layer at said surface abutting said offset spacer at said each end;
a source/drain extension under each said source/drain spacer, the portion of a respective said epi layer under said each source/drain spacer forming each said source/drain extension; and
a source/drain diffusion region formed in said epi layer and said recess at said each source/drain extension, wherein the source/drain spacers above said each source/drain extension delimit said source/drain regions.

13. The semiconductor structure according to claim 12 , wherein the epi layer has a thickness of from 5 to 30 nm.

14. The semiconductor structure according to claim 12 , wherein the epi layer has a thickness of from 5 to 15 nm.

15. The semiconductor structure according to claim 12 , further comprising a gate dielectric on said surface of the semiconductor substrate beneath the transistor gate electrode.

16. The semiconductor structure according to claim 15 , wherein the gate dielectric is an insulating material selected from an oxide, nitride, or oxynitride.

17. The semiconductor structure according to claim 15 , wherein the gate dielectric is nitride SiO 2 or oxynitride.

18. The semiconductor structure according to claim 15 , wherein the transistor gate electrode comprises doped silicon.

19. The semiconductor structure according to claim 15 , wherein the semiconductor substrate comprises silicon, SiGe, SiC, SiGeC, or a combination thereof.

20. The semiconductor structure according to claim 15 , wherein the semiconductor substrate is a silicon-on-silicon substrate.

Assignees

• Doris Bruce B
• Faltermeier Johnathan E
• Adam Lahir M Shaik
• Haran Balasubramanian S Pranatharthi
• Globalfoundries Inc

Inventors

• Doris Bruce B
• Faltermeier Johnathan E
• Adam Lahir M Shaik
• Haran Balasubramanian S Pranatharthi

Classifications

• H10P32/171

  being group IV material · CPC title

• H10P32/12

  between a solid phase and a gaseous phase · CPC title

• H10P30/225

  of a molecular ion, e.g. decaborane · CPC title

• H10P30/222

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title