Split-gate non-volatile memory cells having gap protection zones

Patent metadata

Field	Value
Publication number	US-9331160-B2
Application number	US-201313970796-A
Country	US
Kind code	B2
Filing date	Aug 20, 2013
Priority date	Aug 20, 2013
Publication date	May 3, 2016
Grant date	May 3, 2016

Abstract

Split-gate non-volatile memory (NVM) cells having gap protection zones are disclosed along with related manufacturing methods. After formation of a gate for a split-gate NVM cell over a substrate, a doped region is formed adjacent the gate. A first portion of the doped region is then removed to leave a second portion of the doped region that forms a gap protection zone adjacent the gate. For some disclosed embodiments, a select gate is formed before a control gate. For other disclosed embodiments, the control gate is formed before the select gate. The gap protection zones can be formed, for example, using an etch processing step to remove the desired portions of the doped region, and a spacer can also be used to protect the gap protection zone during this etch processing step. Related NVM systems are also disclosed.

First claim

What is claimed is:

1. A method for forming a non-volatile memory (NVM) cell having a gap protection zone, comprising:
forming a gate for a split-gate non-volatile memory (NVM) cell over a substrate;
forming a doped region within the substrate adjacent the gate using at least one of a p-type dopant or an n-type dopant; and
removing a first portion of the doped region to leave a second portion of the doped region within the substrate adjacent the gate, the second portion providing a gap protection zone region;
wherein before the forming a doped region step, the method further comprises forming a halo doped region adjacent the gate using a directional implant processing step, the halo doped region being deeper than the gap protection zone region, having a lower doping concentration than the gap protection zone region, and having an opposite dopant type from the gap protection zone region.

2. The method of claim 1 , wherein the gate is a select gate, and further comprising forming a charge storage layer adjacent the select gate and at least in part over the gap protection zone region, and also forming a control gate adjacent the charge storage layer such that the gap protection zone region is located within the substrate between the control gate and the substrate below the select gate.

3. The method of claim 1 , wherein the gate is a control gate formed on top of a charge storage layer, and further comprising forming a dielectric layer adjacent the control gate and at least in part over the gap protection zone region, and also forming a select gate adjacent the dielectric layer such that the gap protection zone region is located within the substrate between the select gate and the substrate below the control gate.

4. The method of claim 1 , wherein once formed, the gap protection zone region comprises an average doping concentration of above about 1×10 18 atoms per cubic centimeter.

5. The method of claim 1 , wherein the gap protection zone region is formed using an ion implant having an energy range of 1 to 10 keV (kilo-electron volt) and a dose of 1×10 13 to 1×10 14 atoms per square centimeter.

6. The method of claim 1 , wherein after the forming steps and prior to the removing step, the method further comprises forming a spacer adjacent the gate to protect the gap protection zone region during the removing step.

7. The method of claim 6 , wherein the removing step comprises an etch processing step, and wherein the spacer protects the gap protection zone region during the etch processing step, and further comprising removing the spacer with a spacer etch processing step.

8. The method of claim 1 , wherein the removing step comprises a directional etch processing step, and wherein no spacer is utilized to protect the gap protection zone region during the directional etch processing step.

9. The method of claim 1 , wherein the removing step also leaves a tail portion of the doped region extending laterally from the gap protection zone region and having a thickness less than the gap protection zone region.

10. The method of claim 1 , wherein the halo doped region comprises an average doping concentration of below about 1×10 18 atoms per cubic centimeter, and wherein the gap protection zone region comprises an average doping concentration of above about 1×10 18 atoms per cubic centimeter.

11. The method of claim 1 , wherein the gap protection zone region is located adjacent only one edge of the gate.

12. The method of claim 1 , wherein the gap protection zone region is a doped monocrystalline material.

13. The method of claim 1 , wherein the substrate has a first dopant type and the gap protection zone region has a second opposite dopant type.

14. The method of claim 1 , wherein substrate has a first dopant type and gap protection zone region has a same dopant type.

Assignees

• Loiko Konstantin V
• Williams Spencer E
• Winstead Brian A
• Freescale Semiconductor Inc

Inventors

• Loiko Konstantin V
• Williams Spencer E
• Winstead Brian A

Classifications

• H10D30/6893

  wherein the floating gate has multiple non-connected parts, e.g. multi-particle floating gate · CPC title

• H10D30/696

  having at least one additional gate, e.g. program gate, erase gate or select gate · CPC title

• H10D30/681

  having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688) · CPC title

• H10D30/0413

  of FETs having charge-trapping gate insulators, e.g. MNOS transistors · CPC title

• H10D30/0411

  of FETs having floating gates · CPC title