Fabrication of a silicon structure and deep silicon etch with profile control

Patent metadata

Field	Value
Publication number	US-9330926-B2
Application number	US-33895008-A
Country	US
Kind code	B2
Filing date	Dec 18, 2008
Priority date	Dec 21, 2007
Publication date	May 3, 2016
Grant date	May 3, 2016

Abstract

A method of etching features into a silicon layer with a steady-state gas flow is provided. An etch gas comprising an oxygen containing gas and a fluorine containing gas is provided. A plasma is provided from the etch gas. Then, the flow of the etch gas is stopped.

First claim

What is claimed is:

1. A method of etching features into at least one conductive layer, at least one dielectric layer, and into a silicon substrate through a patterned mask, comprising:
a) loading a wafer into a process chamber, wherein the patterned mask, the at least one conductive layer and the at least one dielectric layer are disposed over the silicon substrate;
b) etching at least one conductive layer through the patterned mask, comprising
flowing a conductive layer etch gas into the process chamber;
forming a plasma from the conductive layer etch gas;
etching the at least one conductive layer with the plasma formed from the conductive layer etch gas such that the at least one conductive layer is patterned to have the features therein; and
stopping the conductive layer etch gas flow;

c) etching at least one dielectric layer through the patterned mask, comprising:
flowing a dielectric layer etch gas into the process chamber;
forming a plasma from the dielectric layer etch gas;
etching the at least one dielectric layer with the plasma formed from the dielectric layer etch gas such that the at least one dielectric layer is patterned to have the features therein; and
stopping the dielectric layer etch gas flow;

d) etching the silicon substrate through the patterned mask, the at least one patterned conductive layer, and the at least one patterned dielectric layer, comprising:
flowing a silicon etch gas into the chamber;
forming a plasma from the silicon etch gas;
etching into the silicon substrate with the plasma formed from the silicon etch gas; and
stopping the silicon etch gas flow; and

e) unloading the wafer from the process chamber,
wherein a temperature of a chuck supporting the silicon substrate is maintained in a range between −10° C. and +10° C. during the etching of the at least one conductive layer and the etching of the silicon substrate.

2. The method of claim 1 , wherein the at least one conductive layer is a metal-containing layer.

3. The method of claim 1 , wherein the at least one dielectric layer is a silicon-containing layer.

4. The method of claim 1 , further comprising providing a pre-etch treatment in the same chamber, after loading the wafer into the process chamber and prior to the etching, comprising:
providing a pre-etch treatment gas;
forming a plasma from the pre-etch treatment gas; and
treating the wafer surface with the plasma formed from the pre-etch treatment gas.

5. The method of claim 4 , wherein the plasma from the pre-etch treatment gas removes defects present in the surface of the exposed layer.

6. The method of claim 1 , wherein a plurality of conductive layers and a plurality of dielectric layers are alternately disposed over the silicon substrate, and steps b and c are repeated in an alternating manner at least twice.

7. The method of claim 1 , further comprising providing a post-etch treatment in the same chamber, after etching of the silicon substrate and before unloading the wafer, comprising:
providing a post-etch treatment gas into the chamber;
forming a plasma from the post-etch treatment gas; and
treating the wafer surface with the plasma formed from the post-etch treatment gas.

8. The method of claim 7 , wherein the plasma from the post-etch treatment gas removes the patterned mask remaining on the wafer without removing the at least one patterned conductive layer and the at least one patterned dielectric layer.

9. The method of claim 7 , wherein the plasma from the post-etch treatment gas removes the patterned mask remaining after completing said etching the silicon substrate, and wherein the wafer remains in the process chamber after the loading, during performing steps b), c), and the post-etch treatment, until the unloading.

10. The method of claim 1 , wherein the temperature of the chuck supporting the silicon substrate is maintained in a range between −10° C. and +10° C. during the etching of the at least one dielectric layer.

11. The method of claim 1 , wherein the temperature of the chuck supporting the silicon substrate is maintained in a range between −10° C. and +10° C. during the etching of the at least one dielectric layer if the dielectric layer is a silicon oxide dielectric layer, and a range between −10° C. and +60° C. if the dielectric layer is a low-k dielectric layer.

12. The method of claim 1 , wherein the silicon substrate is etched with a steady-state gas flow comprising SF 6 , O 2 , SiF 4 , and HBr.

13. The method of claim 1 , wherein the at least one conductive layer includes a metal-containing conductive layer and a silicon containing conductive layer.

14. A method of etching features into at least two conductive layers, at least two dielectric layers, and into a silicon substrate through a patterned mask, comprising:
a) loading a wafer into a process chamber, wherein, the at least two conductive layers and the at least two dielectric layers are alternately disposed over the silicon substrate;
b) etching a conductive layer through the patterned mask, comprising
flowing a conductive layer etch gas into the process chamber;
forming a plasma from the conductive layer etch gas;
etching the conductive layer with the plasma formed from the conductive layer etch gas such that the conductive layer is patterned to have the features therein; and
stopping the conductive layer etch gas flow;

c) etching a dielectric layer through the patterned mask, comprising:
flowing a dielectric layer etch gas into the process chamber;
forming a plasma from the dielectric layer etch gas;
etching the dielectric layer with the plasma formed from the dielectric layer etch gas such that the dielectric layer is patterned to have the features therein; and
stopping the dielectric layer etch gas flow;

d) repeating steps b) and c) in an alternating manner at least twice;
e) etching the silicon substrate, after completing step d), through the patterned mask, patterned conductive layers, and patterned dielectric layers, comprising:
flowing a silicon etch gas into the chamber;
forming a plasma from the silicon etch gas;
etching into the silicon substrate with the plasma formed from the silicon etch gas; and
stopping the silicon etch gas flow; and

f) unloading the wafer from the process chamber,
wherein a temperature of a chuck supporting the silicon substrate is maintained in a range between −10° C. and +10° C. during at the etching of the conductive layer and the etching of the silicon substrate.

15. The method of claim 14 , wherein the at least one conductive layer includes a surface conductive layer below the patterned mask and a conductive device layer below a dielectric layer.

16. The method of claim 15 , wherein the at least one dielectric layer includes the dielectric layer below the surface conductive layer and a dielectric device layer below the conductive device layer.

17. The method as recited in claim 14 , wherein said etching the silicon substrate further comprises:
providing a bias voltage.

18. The method as recited in claim 14 , wherein in said etching the silicon substrate, an aspect ratio of the features is at least 80.

19. The method as recited in claim 14 , wherein in said etching the silicon substrate, a depth of the features is at least 80 μm.

20. The method as recited in claim 14 , wherein the silicon etch gas comprises an oxygen containing gas and a fluorine containing gas.

21. The method as recited in claim 20 , wherein the oxygen containing gas comprises at least one

Assignees

• Chebi Robert
• Lin Frank
• Winniczek Jaroslaw W
• Chen Wan-Lin
• Mcdonnell Erin
• Zheng Lily
• Lassig Stephan
• Bogart Jeff
• Rusu Camelia
• Lam Res Corp

Inventors

• Chebi Robert
• Lin Frank
• Winniczek Jaroslaw W
• Chen Wan-Lin
• Mcdonnell Erin
• Zheng Lily
• Lassig Stephan
• Bogart Jeff
• Rusu Camelia

Classifications

• H10P70/20

  Cleaning during device manufacture · CPC title

• H10P50/287

  by chemical means · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/268

  of silicon-containing layers · CPC title

• H10P50/267

  using plasmas · CPC title