Write and read common leveling for 4-bit wide drams
US-11456052-B1 · Sep 27, 2022 · US
US9208902B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9208902-B2 |
| Application number | US-60810109-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 29, 2009 |
| Priority date | Oct 31, 2008 |
| Publication date | Dec 8, 2015 |
| Grant date | Dec 8, 2015 |
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An integrated circuit containing a memory and a sense amplifier. The integrated circuit also containing an extended delay circuit which extends the delay between when a precharged bitline is floated and when a wordline is enabled. A method of testing an integrated circuit to identify bitlines with excessive leakage.
Opening claim text (preview).
What is claimed is: 1. An integrated circuit, comprising: a memory array; and an extended delay circuit that, in a testing mode, inserts a write extended delay between when a precharged bitline is floated and when a wordline is enabled during a write operation, and that does not insert the write extended delay during a write operation in normal operation. 2. The integrated circuit of claim 1 wherein said memory array is an SRAM array.…
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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