Bitline leakage detection in memories

US9208902B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9208902-B2
Application numberUS-60810109-A
CountryUS
Kind codeB2
Filing dateOct 29, 2009
Priority dateOct 31, 2008
Publication dateDec 8, 2015
Grant dateDec 8, 2015

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  2. Abstract

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  5. First independent claim

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Abstract

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An integrated circuit containing a memory and a sense amplifier. The integrated circuit also containing an extended delay circuit which extends the delay between when a precharged bitline is floated and when a wordline is enabled. A method of testing an integrated circuit to identify bitlines with excessive leakage.

First claim

Opening claim text (preview).

What is claimed is: 1. An integrated circuit, comprising: a memory array; and an extended delay circuit that, in a testing mode, inserts a write extended delay between when a precharged bitline is floated and when a wordline is enabled during a write operation, and that does not insert the write extended delay during a write operation in normal operation. 2. The integrated circuit of claim 1 wherein said memory array is an SRAM array.…

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What does patent US9208902B2 cover?
An integrated circuit containing a memory and a sense amplifier. The integrated circuit also containing an extended delay circuit which extends the delay between when a precharged bitline is floated and when a wordline is enabled. A method of testing an integrated circuit to identify bitlines with excessive leakage.
Who is the assignee on this patent?
Pious Beena, Deng Xiaowei, Loh Wah Kit, and 2 more
What technology area does this patent fall under?
Primary CPC classification G11C29/842. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Dec 08 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).