Peak current management in multi-die non-volatile memory devices

Patent metadata

Field	Value
Publication number	US-9329986-B2
Application number	US-201313785720-A
Country	US
Kind code	B2
Filing date	Mar 5, 2013
Priority date	Sep 10, 2012
Publication date	May 3, 2016
Grant date	May 3, 2016

Abstract

Techniques are presented to operate a greater number of dice in parallel while not exceeding peak current limits. The device can arbitrate between multiple dice and, when needed, suspend operations on one or more dice in a way to average the chance of performance penalty so that all chips will proceed with write at an equal probability. In other aspects, the suspension of operations can be weighted based on factors such as the relative speed of the different dice or differing loads.

First claim

The invention claimed is:

1. A non-volatile memory system comprising:
a plurality of non-volatile memory integrated circuits, each including:
one or more memory arrays of non-volatile memory cells;
read and write circuitry connected to the one or more memory arrays; and
a state machine connected to the read and write circuitry, wherein the state machine assigns an index corresponding to an amount of current expected to be drawn for each of one or more upcoming operations of the plurality of non-volatile memory integrated circuits prior to initiation thereof based on a phase of the state machine;

a controller integrated circuit to control transfer of data between the plurality of non-volatile memory integrated circuits and a host device that is connected to the non-volatile memory system and to manage storage of data in the non-volatile memory system;
a bus structure connected to the controller integrated circuit and the plurality of non-volatile memory integrated circuits for the transfer of data and commands therebetween; and
arbitration logic connected to receive the index assigned by the state machine, wherein the arbitration logic can selectively issue pause commands to the plurality of non-volatile memory integrated circuits based upon the index in order to maintain current used by the non-volatile memory system under a first value.

2. The non-volatile memory system of claim 1 , wherein the arbitration logic is on the controller integrated circuit.

3. The non-volatile memory system of claim 1 , wherein the arbitration logic is on one of the plurality of non-volatile memory integrated circuits.

4. The non-volatile memory system of claim 1 , wherein the state machine assigns the index based on a relative amount of current drawn by expected phases of scheduled operations, wherein a higher index corresponds to a greater expected current.

5. The non-volatile memory system of claim 4 , wherein bit line charging is a high index phase.

6. The non-volatile memory system of claim 4 , wherein a sense phase is a medium index phase.

7. The non-volatile memory system of claim 4 , wherein a data transfer is a high index phase.

8. The non-volatile memory system of claim 4 , wherein the index includes a priority value, wherein the priority value is used in determining the pause commands.

9. The non-volatile memory system of claim 4 , wherein the index includes an indication of whether the upcoming operations are read or write operations, wherein the indication is used in determining the pause commands.

10. The non-volatile memory system of claim 4 , wherein the index includes a cycle number for write operations, wherein the cycle number is used in determining the pause commands.

11. The non-volatile memory system of claim 1 , wherein the index includes an indication of whether an operation is not pausable.

12. The non-volatile memory system of claim 1 , wherein the pause commands are issued based on a round robin algorithm.

13. The non-volatile memory system of claim I, wherein the arbitration logic orders the plurality of non-volatile memory integrated circuits based on the index, wherein the pause commands are issued based on the order.

14. The non-volatile memory system of claim 1 , wherein the arbitration logic includes the amount of current used in the bus structure in determining to issue the pause commands in order to maintain the current used by the non-volatile memory system under the first value.

15. The non-volatile memory system of claim 1 , wherein the arbitration logic further includes the amount of current used in the controller integrated circuit in determining the issuing of the pause commands in order to maintain the current used by the non-volatile memory system under the first value.

16. The non-volatile memory system of claim 1 , wherein the controller integrated circuit includes an Input/Output (IO) interface to transfer data between the non-volatile memory system and the host device, wherein the arbitration logic includes the amount of current used in the IO interface in determining to issue the pause commands in order to maintain the current used by the non-volatile memory system under the first value.

17. A non-volatile memory system comprising:
a plurality of non-volatile memory integrated circuits, each including one or more memory arrays with read and write circuitry connected thereto operated according to a state machine formed thereupon, wherein the state machine assigns an index corresponding to an amount of current expected to be drawn for upcoming operations of the plurality of non-volatile memory integrated circuits based on a phase of the state machine;
a controller integrated circuit to control transfer of data between the plurality of non-volatile memory integrated circuits and a host device that is connected to the non-volatile memory system and to manage storage of data in the non-volatile memory system;
a bus structure connected to the controller integrated circuit and the plurality of non-volatile memory integrated circuits for the transfer of data and commands therebetween; and
arbitration logic connected to receive the index assigned by the state machine, where the arbitration logic can selectively issue pause commands to the plurality of non-volatile memory integrated circuits based upon the index in order to maintain current used by the non-volatile memory system under a first value, wherein the arbitration logic is on the controller integrated circuit and the controller integrated circuit further includes load analyzing circuitry to determine a load for each of the plurality of non-volatile memory integrated circuits, and wherein the arbitration logic includes the load for each of the plurality of non-volatile memory integrated circuits in determining the issuing of the pause commands in order to maintain the current used by the non-volatile memory system under the first value.

18. A non-volatile memory system comprising:
a plurality of non-volatile memory integrated circuits, each including one or more memory arrays with read and write circuitry connected thereto operated according to a state machine formed thereupon, wherein the state machine assigns an index corresponding to an amount of current expected to be drawn for upcoming operations of the plurality of non-volatile memory integrated circuits based on a phase of the state machine;
a controller integrated circuit to control transfer of data between the plurality of non-volatile memory integrated circuits and a host device that is connected to the non-volatile memory system and to manage storage of data in the non-volatile memory system;
a bus structure connected to the controller integrated circuit and the plurality of non-volatile memory integrated circuits for the transfer of data and commands therebetween; and
arbitration logic connected to receive the index assigned by the state machines, where the arbitration logic can selectively issue pause commands to the plurality of non-volatile memory integrated circuits based upon the index in order to maintain current used by the non-volatile memory system under a first value, wherein each of the plurality of non-volatile memory integrated circuits further includes speed analysis circuitry to determine a relative speed of operation thereof, and wherein the arbitration logic includes the relative speed of operation for each of the plurality of non-volatile memory integrated circuits in determining the issuing of the pause commands in order to maintain the current used by the non-volatile memory system under the first va

Assignees

• Sandisk Technologies Inc

Inventors

• Li Yan
• Duzly Yacov
• Tsai Frank Wanfang
• Marcu Alon

Classifications

• G11C16/30

  Power supply circuits · CPC title

• G11C5/14 Primary

  Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} · CPC title

• G06F12/00 Primary

  Accessing, addressing or allocating within memory systems or architectures (digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06) · CPC title