Multiple data rate memory interface architecture

Patent metadata

Field	Value
Publication number	US-9224438-B2
Application number	US-201313925173-A
Country	US
Kind code	B2
Filing date	Jun 24, 2013
Priority date	May 27, 2004
Publication date	Dec 29, 2015
Grant date	Dec 29, 2015

Abstract

The present invention provides a DQS bus for implementing high speed multiple-data-rate interface architectures in programmable logic devices. The DQS bus has a balanced tree structure between at least one data strobe circuit and a plurality of I/O register blocks.

First claim

We claim:

1. An integrated circuit comprising:
a group of register blocks;
a plurality of strobe circuits, wherein each of the plurality of strobe circuits is pre-configured to accommodate a respective memory width; and
selection circuitry coupled to the group of register blocks, wherein:
in response to a first input of the selection circuitry being selected, the group of register blocks is configured to be driven by a first strobe circuit from the plurality of strobe circuits to accommodate a first memory width, and
in response to a second input of the selection circuitry being selected, the group of register blocks is configured to be driven by a second strobe circuit from the plurality of strobe circuits, different from the first strobe circuit, to accommodate a second memory width that is different from the first memory width.

2. The integrated circuit of claim 1 , wherein the first memory width is less than or equal to a number of register blocks in the group of register blocks and the second memory width is greater than the number of register blocks in the group of register blocks.

3. The integrated circuit of claim 1 , further comprising a second group of register blocks, wherein when the first input of the selection circuitry is selected, the second group of register blocks is configured to be driven by the second strobe circuit and when the second input of the selection circuitry is selected, the second group of register blocks is configured to be driven by the second strobe circuit.

4. The integrated circuit of claim 1 , wherein:
in response to the first input of the selection circuitry being selected, the group of register blocks is configured to be driven by the first strobe circuit through a first path comprising a first number of buffers; and
in response to the second input of the selection circuitry being selected, the group of register blocks is configured to be driven by the second strobe circuit through a second path comprising a second number of buffers that is different from the first number of buffers.

5. The integrated circuit of claim 4 , wherein at least one of the buffers comprises an inverter.

6. The integrated circuit of claim 1 , wherein the selection circuitry is coupled to at least one register block from the group of register blocks through an interconnect having a balanced tree structure.

7. The integrated circuit of claim 1 , wherein:
in response to the first input of the selection circuitry being selected, the group of register blocks is configured to be driven by the first strobe circuit through a first interconnect having a first balanced tree structure; and
in response to the second input of the selection circuitry being selected, the group of register blocks is configured to be driven by the second strobe circuit through a second interconnect having a second balanced tree structure that is different from the first balanced tree structure.

8. The integrated circuit of claim 7 , wherein:
the first strobe circuit is connected to the first and a second group of register blocks;
the first balanced tree structure includes a first signal path having a first length from the first strobe circuit to a midpoint of the first group of register blocks;
the second balanced tree structure includes a second signal path having a second length from the first strobe circuit to a midpoint of the second group of register blocks; and
the first length is approximately equal to the second length.

9. The integrated circuit of claim 1 , wherein the selection circuitry comprises at least one multiplexer configurable by setting at least one configuration bit in the integrated circuit.

10. A method of configuring an integrated circuit device comprising a group of register blocks, the method comprising:
configuring logic of said integrated circuit device as selection circuitry coupled to the group of register blocks and a plurality of strobe circuits, wherein each of the plurality of strobe circuits is pre-configured to accommodate a respective memory width, and wherein:
in response to a first input of the selection circuitry being selected, the group of register blocks is driven by a first strobe circuit from the plurality of strobe circuits to accommodate a first memory width, and
in response to a second input of the selection circuitry being selected, the group of register blocks is driven by a second strobe circuit from the plurality of strobe circuits, different from the first strobe circuit, to accommodate a second memory width that is different from the first memory width.

11. The method of claim 10 , wherein the first memory width is less than or equal to a number of register blocks in the group of register blocks and the second memory width is greater than the number of register blocks in the group of register blocks.

12. The method of claim 10 , wherein the integrated circuit device further comprises a second group of register blocks, wherein when the first input of the selection circuitry is selected, the second group of register blocks is driven by the second strobe circuit and when the second input of the selection circuitry is selected, the second group of register blocks is driven by the second strobe circuit.

13. The method of claim 10 , the method further comprising:
configuring the group of register blocks to be driven by the first strobe circuit through a first path comprising a first number of buffers, in response to the first input of the selection circuitry being selected; and
configuring the group of register blocks to be driven by the second strobe circuit through a second path comprising a second number of buffers that is different from the first number of buffers, in response to the second input of the selection circuitry being selected.

14. The method of claim 13 , wherein at least one of the buffers comprises an inverter.

15. The method of claim 10 , the method further comprising coupling the first strobe circuit to at least one register block from the group of register blocks through an interconnect having a balanced tree structure.

16. The method of claim 10 , the method further comprising:
configuring the group of register blocks to be driven by the first strobe circuit through a first interconnect having a first balanced tree structure, in response to the first input of the selection circuitry being selected; and
configuring the group of register blocks to be driven by the second strobe circuit through a second interconnect having a second balanced tree structure that is different from the first balanced tree structure, in response to the second input of the selection circuitry being selected.

17. The method of claim 16 , the method further comprising connecting the first strobe circuit to the first and a second group of register blocks, wherein:
the first balanced tree structure includes a first signal path having a first length from the first strobe circuit to a midpoint of the first group of register blocks;
the second balanced tree structure includes a second signal path having a second length from the first strobe circuit to a midpoint of the second group of register blocks; and
the first length is approximately equal to the second length.

18. The method of claim 10 , wherein the selection device comprises a multiplexer, said method further comprising configuring the multiplexer by setting at least one configuration bit in the programmable integrated circuit device.

19. A memory interface comprising:
a group of register blocks;
a plurality of strobe circuits, where

Assignees

• Altera Corp

Inventors

• Lee Andy L
• Johnson Brian D

Classifications

• G11C7/10 Primary

  Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers · CPC title

• H03K19/17744 Primary

  for input/output signals · CPC title