Semiconductor device manufacturing method

Patent metadata

Field	Value
Publication number	US-9324857-B2
Application number	US-201514683203-A
Country	US
Kind code	B2
Filing date	Apr 10, 2015
Priority date	Aug 3, 2011
Publication date	Apr 26, 2016
Grant date	Apr 26, 2016

Abstract

A semiconductor device includes a p-type semiconductor layer, n-type column regions formed of columnar thermal donors exhibiting an n-type property, a p-type column region interposed between the n-type column regions, the n-type column regions configured to form a super-junction structure in cooperation with the p-type column region, a channel region formed in the semiconductor layer, a source region formed in the channel region, a gate insulator film formed on the semiconductor layer, and a gate electrode formed on the gate insulator film and opposite to the channel region across the gate insulator film.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a p-type semiconductor layer;
n-type column regions arranged in a mutually spaced-apart relationship along a predetermined direction parallel to a front surface of the semiconductor layer, each of the n-type column regions formed of thermal donors exhibiting an n-type property;
a p-type column region of the semiconductor layer interposed between the n-type column regions adjoining to each other, the n-type column regions configured to form a super-junction structure in the semiconductor layer in cooperation with the p-type column region;
a channel region of an n-type or p-type selectively formed in a front surface portion of the semiconductor layer to make up a portion of the front surface of the semiconductor layer;
a source region selectively formed in a front surface portion of the channel region to make up a portion of the front surface of the semiconductor layer, a conductivity type of the source region being opposite to that of the channel region;
a gate insulator film formed on the front surface of the semiconductor layer; and
a gate electrode formed on the gate insulator film and opposite to the channel region across the gate insulator film,
wherein H + particles are selectively irradiated on a plurality of portions of the semiconductor layer to form the n-type column regions formed of thermal donors.

2. The device of claim 1 , wherein the n-type column regions have a specific resistance of from 1.0 Ω·cm to 10.0 Ω·cm.

3. The device of claim 1 , wherein the channel region is an n-type and the source region is a p-type, and further comprising:
a p-channel MOSFET configured to induce a channel between the p-type source region and the p-type column region by applying a voltage to the gate electrode.

4. The device of claim 3 , wherein the semiconductor layer includes a p-type base region formed in a direction of a rear surface of the semiconductor layer with respect to the n-type column regions and the p-type column region so as to extend below the n-type column regions and the p-type column region along the predetermined direction parallel to the front surface of the semiconductor layer.

5. The device of claim 1 , wherein the channel region is a p-type and the source region is an n-type, and further comprising:
an n-channel MOSFET configured to induce a channel between the n-type source region and the n-type column regions by applying a voltage to the gate electrode.

6. The device of claim 5 , wherein the semiconductor layer includes an n-type base region formed in a direction of a rear surface of the semiconductor layer with respect to the n-type column region and the p-type column region so as to extend below the n-type column regions and the p-type column region along the predetermined direction parallel to the front surface of the semiconductor layer.

7. The device of claim 1 , wherein the n-type column regions make contact with the channel region.

8. The device of claim 1 , wherein the n-type column regions includes a region formed on a rear surface of the p-type semiconductor layer between the channel region and the n-type column regions spaced apart from the channel region.

9. The device of claim 1 , wherein the selectively irradiating the H + particles is performed between 5 MeV and 10 MeV.

10. The device of claim 1 , wherein the plurality of irradiated portions of the semiconductor layer is annealed at a temperature of from 400 degrees C. to 450 degrees C.

11. The device of claim 1 , wherein the n-type column regions formed of thermal donors are determined by stop positions of the H + particles.

12. The device of claim 1 , wherein a range of each of the n-type column regions formed of thermal donors is determined by controlling an irradiation energy of the H + particles.

13. The device of claim 1 , further comprising a depletion layer formed over an entire interface between each of the n-type column regions and the p-type column region to extend along the direction of the interface.

Assignees

• Rohm Co Ltd

Inventors

• Nakajima Toshio

Classifications

• H10P34/40

  with high-energy radiation · CPC title

• H10P34/20

  for inducing a nuclear reaction transmuting chemical elements · CPC title

• H10P30/208

  of electrically inactive species · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/20

  into semiconductor materials, e.g. for doping · CPC title