Method for controlling the profile of an etched metallic layer

Patent metadata

Field	Value
Publication number	US-9324793-B2
Application number	US-201514871157-A
Country	US
Kind code	B2
Filing date	Sep 30, 2015
Priority date	Feb 24, 2014
Publication date	Apr 26, 2016
Grant date	Apr 26, 2016

Abstract

An ashing chemistry employing a combination of Cl 2 and N 2 is provided, which removes residual material from sidewalls of a patterned metallic hard mask layer without residue such that the sidewalls of the patterned metallic hard mask layer are vertical. The vertical profiled of the sidewalls of the patterned metallic hard mask layer can be advantageously employed to reduce pattern factor dependency in the etch bias between the pattern transferred into an underlying layer and the pattern as formed on the metallic hard mask layer. Further, the ashing chemistry can be employed to enhance removal of stringers in vertical portions of a metallic material layer.

First claim

What is claimed is:

1. A method of patterning a structure, said method comprising:
forming a vertical stack, from bottom to top, comprising at least a gate dielectric layer, a metallic material layer, an organic planarization layer (OPL), and a photoresist layer on a planar top surface and a recessed horizontal surface that are provided on, or over, a substrate;
lithographically patterning said photoresist layer;
etching said OPL and said metallic material layer employing at least one anisotropic etch that employs said patterned photoresist layer as an etch mask;
etching physically exposed portions of said gate dielectric layer; and
simultaneously removing a residual portion of said OPL and a vertical portion of said metallic material layer over said recessed horizontal surface employing an ashing process, said ashing process employing a combination of Cl 2 and N 2 to remove said OPL and said vertical portion of said metallic material layer.

2. The method of claim 1 , wherein said vertical stack further comprises a semiconductor material layer overlying said metallic material layer and underlying said OPL, wherein said at least one anisotropic etch transfers said pattern through said semiconductor material layer.

3. The method of claim 1 , wherein said metallic material layer comprises a conductive metallic nitride material.

4. The method of claim 1 , wherein said patterned photoresist is removed simultaneously with said OPL during said ashing process.

5. The method of claim 1 , wherein said vertical portion of said metallic material layer contact a vertical portion of said gate dielectric layer.

6. The method of claim 1 , wherein processing gases employed for said ashing process does not include oxygen atoms, oxygen ions, oxygen molecules, ozone ions, or ozone molecules.

7. The method of claim 1 , wherein said ashing process is performed at a pressure range from 1 mTorr to 300 mTorr and at a temperature from −20° C. to 400° C.

8. The method of claim 1 , wherein said Cl 2 is introduced into a process chamber at a flow rate from 1 sccm to 300 sccm and said N 2 is introduced into said process chamber at a flow rate from 100 sccm to 300 sccm.

9. The method of claim 1 , wherein said etching physically exposed portions of said gate dielectric layer comprises a wet etch.

10. The method of claim 1 , wherein said gate dielectric layer comprises silicon oxide, silicon oxynitride or a dielectric metal oxide having a dielectric constant of greater than 8.0.

11. The method of claim 1 , wherein one of said planar top surface and said recessed horizontal surface is a semiconductor surface, and another of said planar top surface and said recessed horizontal surface is a dielectric surface.

12. The method of claim 11 , wherein said dielectric surface is a planar top surface of a shallow trench isolation structure embedded within a substrate that includes a semiconductor material portion, wherein said semiconductor surface is a top surface of said semiconductor material portion.

13. The method of claim 1 , wherein said at least one anisotropic etch comprises a reactive ion etch including at least one etchant selected from a hydrofluorocarbon gas and a hydrochlorocarbon gas.

14. The method of claim 13 , wherein said at least one etchant comprises CH 2 F 2 , CHF 3 , CCl 2 F 2 , CHCl 2 or any mixture thereof.

15. The method of claim 1 , wherein during said at least one anisotropic etching of said metallic hard mask layer an organo-metallic passivation spacer is formed on sidewalls of an opening in said metallic hard mask layer.

16. The method of claim 15 , wherein said organo-metallic passivation spacer comprises a compound comprising a same metallic material as said metallic hard mask layer and a halogen.

17. The method of claim 16 , wherein prior to said ashing said organo-metallic passivation spacer is removed by a wet etch process.

Assignees

• IBM
• St Microelectronics Inc

Inventors

• Clevenger Lawrence A
• Radens Carl J
• Wise Richard S
• Wornyo Edem
• Xu Yiheng
• Zhang John

Classifications

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P70/273 Primary

  the processing being a delineation of conductive layers, e.g. by RIE · CPC title

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10P50/694

  characterised by their behaviour during the process, e.g. soluble masks or redeposited masks · CPC title

• H10P50/287

  by chemical means · CPC title