Die substrate assembly and method

Patent metadata

Field	Value
Publication number	US-9324674-B2
Application number	US-201414562129-A
Country	US
Kind code	B2
Filing date	Dec 5, 2014
Priority date	Dec 24, 2013
Publication date	Apr 26, 2016
Grant date	Apr 26, 2016

Abstract

A die comprising a body of semiconductor material, said body configured to receive a solder layer of gold containing alloy for use in die bonding said die to a substrate, wherein the die includes an interface layer on a surface of the body for receiving the solder layer, the interface layer having a plurality of sub-layers of different metals.

First claim

The invention claimed is:

1. A package comprising a substrate of copper coupled to a die by a solder layer, the solder layer comprising an alloy of gold and tin, the die comprising:
a body of semiconductor material,
wherein the die includes an interface layer on a surface of the body, and the solder layer is affixed to the interface layer;
the interface layer includes a plurality of sub-layers of different metals;
the interface layer comprises a first sub-layer of gold applied to the body, a second sub-layer of silver, a third sub-layer of nickel and a fourth sub-layer of gold; and
the second sub-layer of silver is thinner than the third sub-layer of nickel.

2. The package according to claim 1 , wherein the first sub-layer and fourth sub-layer are thicker than the second and third sub-layers.

3. The package according to claim 2 , wherein the solder layer is at least two times thicker than the interface layer.

4. The package according to claim 1 , wherein the substrate is substantially homogeneous.

5. The package according to claim 1 , wherein the substrate includes a pad layer of gold arranged between the substrate and the solder layer.

6. The package according to claim 1 , wherein the package comprises an RF power package.

7. A method of forming a package, comprising the steps of:
receiving a substrate of copper;
receiving a semiconductor body;
applying an interface layer to the semiconductor body, the interface layer comprising a plurality of sub-layers of different metals,
wherein the step of applying the interface layer comprises:
applying a first sub-layer of gold to the semiconductor body,
applying a second sub-layer of silver to the first sub-layer,
applying a third sub-layer of nickel to the second sub-layer and
applying a fourth sub-layer of gold to the third sub-layer; and

wherein the second sub-layer of silver is thinner than the third sub-layer of nickel; and
die bonding the semiconductor body with the interface layer to the substrate using a solder layer that comprises an alloy of gold and tin.

8. A method according to claim 7 , wherein the step of applying the interface layer comprises sputtering, evaporative plating or electroplating said layer.

9. The method according to claim 7 , wherein the substrate comprises a pad layer of gold thereon for receiving the solder layer.

Assignees

• Nxp Bv
• Ampleon Netherlands Bv

Inventors

• Van Rijckevorsel Johannes Wilhelmus
• De Bruin Emiel

Classifications

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/07355

  changes in materials · CPC title

• H10W72/07336

  Soldering or alloying · CPC title

• H10W72/07333

  Ultrasonic bonding, e.g. thermosonic bonding · CPC title