Processing system with synchronization instruction

Patent metadata

Field	Value
Publication number	US-9323714-B2
Application number	US-201314051140-A
Country	US
Kind code	B2
Filing date	Oct 10, 2013
Priority date	Dec 6, 2012
Publication date	Apr 26, 2016
Grant date	Apr 26, 2016

Abstract

Embodiments of a multi-processor array are disclosed that may include a plurality of processors, and controllers. Each processor may include a plurality of processor ports and a sync adapter. Each sync adapter may include a plurality of adapter ports. Each controller may include a plurality of controller ports, and a configuration port. The plurality of processors and the plurality of controllers may be coupled together in an interspersed arrangement, and the controllers may be distinct from the processors. Each processor may be configured to send a synchronization signal through its adapter ports to one or more controllers, and to pause execution of program instructions while waiting for a response from the one or more controllers.

First claim

What is claimed is:

1. A system, comprising:
a plurality of processors, wherein each processor of the plurality of processors includes a plurality of processor ports and a synchronization adapter, wherein the synchronization adapter includes a plurality of adapter ports;
a plurality of controllers, wherein each controller of the plurality of controllers includes a plurality of controller ports, wherein each controller port of the plurality of controller ports is coupled to adapter port of a neighboring processor of the plurality of processors;
wherein each processor of the plurality of processors is configured to:
send, selectively, a synchronization signal through one or more adapter ports to a respective one or more controllers of the plurality of controllers; and
pause execution of program instructions dependent upon a response from the one or more controllers;

wherein each controller of the plurality of controllers is configured to:
receive one or more synchronization signals from a respective one or more processors of the plurality of processors; and
send a response to each of the respective one or more processors of the plurality of processors dependent upon the received one or more synchronization signals.

2. The system of claim 1 , wherein each controller of the plurality of controllers includes a configuration port configured to receive one or more configuration data bits.

3. The system of claim 2 , wherein to send the response to each of the respective one or more processors, each controller of the plurality of controllers is further configured to send the response to the respective one or more processors dependent upon the one or more configuration data bits.

4. The system of claim 1 , wherein each controller of the plurality of controllers includes a register.

5. The system of claim 4 , wherein the one or more configuration bits for each controller of the plurality of controllers is stored in the register of each controller.

6. A method for operating a multiprocessor system, wherein the multiprocessor system includes a plurality of processors and a plurality of synchronization controllers, wherein each processor of the plurality of processors includes a synchronization adapter, the method comprising:
designing configuration data and software for each group of one or more groups of processors, wherein each group of the one or more groups of processors includes a subset of the plurality of processors, and wherein designing the configuration data and the software includes:
identifying a given group of the one or more groups of processors and at least one location in the software of each processor of the given group for inserting a synchronization barrier;
identifying a synchronization controller of the plurality of synchronization controllers that is coupled with each synchronization adapter of each processor of the given group;
determining configuration data for the identified synchronization controller dependent upon a direction to each synchronization adapter coupled to the identified synchronization controller, wherein the configuration data enables the transmission of a plurality of synchronization signals between the identified synchronization controller and the synchronization adapter of selected processors of the given group; and
inserting a synchronization barrier into each one of the identified locations in the software for each processor of the given group, wherein each synchronization barrier includes a sequence of one or more synchronization instructions, wherein each synchronization instruction includes one or more arguments, and wherein each argument of the one or more arguments specifies a given one of one or more directions of the identified synchronization controller from the synchronization adapter of each processor of the given group;

loading the designed configuration data and software into the multiprocessor system;
executing the loaded software;
pausing execution of each processor of the given group responsive to each processor of the given group executing a given one of the inserted synchronization instructions; and
resuming execution of each processor of the given group responsive to a determination that all processors if the given group have executed a respective one of the inserted synchronization instructions.

7. The method of claim 6 , wherein the determined configuration data includes a plurality of configuration data bits, each data pattern corresponding to each combination of the plurality of configuration data bits corresponds to a direction to the synchronization adapter of a given processor of the given group of processors coupled to the identified synchronization controller.

8. The method of claim 7 , wherein loading configuration data into the multiprocessor system comprises storing the plurality of configuration data bits into a register of the identified synchronization controller.

9. The method of claim 6 , wherein resuming execution of each processor of the given group comprises de-asserting a stall signal by the identified synchronization controller.

10. The method of claim 6 , wherein pausing execution of each processor of the given group comprises asserting synchronization request signal by the synchronization adapter of each processor of the given group.

11. A synchronization controller, comprising:
a register configured to store a plurality of configuration bits, wherein the plurality of configuration bits encode a plurality of data patterns, wherein each data pattern of the plurality of data patterns corresponds to a given one of a plurality of subsets of coupled directions;
one or more logic circuits, wherein each logic circuit of the one or more logic circuits is configured to:
receive one or more synchronization request signals; and
generate a stall signal for at least one processor dependent upon the received one or more synchronization requests and a corresponding data pattern of the plurality of data patterns, wherein the at least one processor is coupled to synchronization controller in a given direction of a corresponding one of the plurality of subsets of coupled directions.

12. The synchronization controller of claim 11 , wherein each entry of the one or more entries includes a latch.

13. The synchronization controller of claim 11 , wherein to generate the stall signal dependent upon the received one or more synchronization requests and the corresponding data pattern of the plurality of data patterns, each logic circuit is further configured to generate one or more stall signals corresponding to the directions of the corresponding one of the plurality of subsets of coupled directions.

14. The synchronization controller of claim 11 , wherein to generate the stall signal dependent upon the received synchronization requests and the corresponding data pattern of the plurality of data patterns, each logic circuit is further configured to generate the stall signal responsive to the assertion of a selected one of the received synchronization signals, wherein the selected one of the received synchronization signals corresponds to the direction of the corresponding data pattern of the plurality of data patterns.

15. The synchronization controller of claim 14 , wherein to generate the stall signal dependent upon the received synchronization requests and the corresponding data pattern of the plurality of data patterns, each logic circuit is further configured to generate the stall signal responsive to a determination that the remaining received synchronization signals are not asserted.

16. A system, comprising:
a plurality of

Assignees

• Coherent Logix Inc

Inventors

• Dobbs Carl S
• Malik Afzal M
• Faulkner Kenneth R
• Solka Michael B

Classifications

• G06F15/76 Primary

  Architectures of general purpose stored program computers (with program plugboard G06F15/08; multicomputers G06F15/16) · CPC title

• G06F9/522 Primary

  Barrier synchronisation · CPC title