Offset compensation for sense amplifiers

Patent metadata

Field	Value
Publication number	US-9322859-B2
Application number	US-201213728637-A
Country	US
Kind code	B2
Filing date	Dec 27, 2012
Priority date	Oct 13, 2010
Publication date	Apr 26, 2016
Grant date	Apr 26, 2016

Abstract

A method of re-offsetting a plurality of amplifier is provided. The method includes testing the plurality of amplifiers based on a re-offset value at bulks of compensation transistors of the plurality of amplifiers; identifying a first group of first amplifiers of the plurality of amplifiers favoring reading a first logic level and/or a second group of second amplifiers of the plurality of amplifiers favoring reading a second logic level different from the first logic level, based on results of the testing step; changing the re-offset value to a new re-offset value; re-offsetting the first group of first amplifiers and/or the second group of second amplifiers based on the new re-offset value; and re-testing the first group of first amplifiers and the second group of second amplifiers.

First claim

What is claimed is:

1. A method of re-offsetting a plurality of amplifiers, comprising:
testing the plurality of amplifiers based on a re-offset value at bulks of compensation transistors of the plurality of amplifiers, wherein testing of each amplifier of the plurality of amplifiers comprises assessing an ability of the amplifier to read a signal at a pair of inputs, the signal representing a first logic level and a second logic level different from the first logic level;
identifying a first group of first amplifiers of the plurality of amplifiers favoring reading the first logic level and/or a second group of second amplifiers of the plurality of amplifiers favoring reading the second logic level, based on results of the testing operation;
changing the re-offset value to a new re-offset value;
re-offsetting the first group of first amplifiers and/or the second group of second amplifiers based on the new re-offset value; and
re-testing the first group of first amplifiers and the second group of second amplifiers.

2. The method of claim 1 , wherein:
re-offsetting the first group of first amplifiers includes, for each first amplifier in the first group of first amplifiers, changing at least one first voltage value at at least one first bulk of at least one first compensation transistor of the each first amplifier; and
re-offsetting the second group of second amplifiers includes, for each second amplifier in the second group of second amplifiers, changing at least one second voltage value at at least one second bulk of at least one second compensation transistor of the each second amplifier.

3. The method of claim 1 , wherein:
identifying the first group of first amplifiers includes providing first data to the first amplifiers and identifying the first amplifiers that fail;
identifying the second group of second amplifiers includes providing second data to the second amplifiers and identifying the second amplifiers that fail; and
the first data is of opposite logic level from the second data.

4. The method of claim 1 , wherein a pair of compensation transistors of the compensation transistors is coupled to a pair of transistors of an amplifier of the plurality of amplifiers that has different threshold voltage values.

5. The method of claim 4 , wherein the pair of transistors of an amplifier of the plurality of amplifiers that has different threshold voltage values is NMOS transistors and the pair of compensation transistors is NMOS or PMOS transistors.

6. A method of re-offsetting a plurality of amplifiers, the method comprising:
applying a first voltage to a bulk of a compensation transistor of each amplifier of the plurality of amplifiers;
assessing an ability of each amplifier of the plurality of amplifiers to read a signal at a pair of inputs, the signal representing a first logic level and a second logic level different from the first logic level;
identifying a first group of amplifiers of the plurality of amplifiers favoring reading the first logic level after the applying the first voltage; and
applying a second voltage, different from the first voltage, to the bulk of the compensation transistor of each amplifier of the first group of amplifiers.

7. The method of claim 6 , wherein each amplifier of the plurality of amplifiers is coupled between a first power supply voltage and a second power supply voltage and the second power supply voltage is lower than the first power supply voltage;
when the compensation transistors of the plurality of the amplifiers are PMOS transistors, the first voltage is equal to the first power supply voltage; and
when the compensation transistors of the plurality of the amplifiers are NMOS transistors, the first voltage is equal to the second power supply voltage.

8. The method of claim 6 , wherein the identifying the first group of amplifiers comprises using a built-in self-test (BIST) circuit to perform operations comprising
comparing the results from each amplifier of the plurality of amplifiers with expected data.

9. The method of claim 6 , further comprising calculating the first voltage using an equation:
V TN =V TO +γ(√{square root over ( V SB +2φ F )}−√{square root over (2φ F )})

where V TN is a threshold voltage of at least one compensation transistor of the compensation transistors of the plurality of amplifiers, V TO is a threshold voltage of the at least one compensation transistor when V SB is zero, γ is a body effect parameter, V SB is a voltage difference between a source and the bulk of the at least one compensation transistor, and 2 φF is a surface potential.

10. The method of claim 6 , wherein the applying the second voltage comprises applying the second voltage to a single compensation transistor.

11. The method of claim 6 , further comprising:
identifying a second group of amplifiers, within the first group of amplifiers, favoring reading the first logic level after the applying the second voltage; and
applying a third voltage, different from the first voltage and the second voltage, to the bulk of the compensation transistor of each amplifier of the second group of amplifiers.

12. The method of claim 11 , wherein the first voltage, the second voltage, and the third voltage are sequentially decreased.

13. The method of claim 11 , wherein the first voltage, the second voltage, and the third voltage are sequentially increased.

14. A method of re-offsetting a group of amplifiers, the method comprising:
setting a re-offset voltage;
applying the re-offset voltage to the group of amplifiers;
assessing an ability of each amplifier of the group of amplifiers to read a signal at a pair of inputs, the signal representing a first logic level and a second logic level different from the first logic level;
identifying a sub-group of amplifiers, within the group of amplifiers, favoring reading the first logic value; and
repeating the setting, applying, assessing, and identifying operations to the sub-group until results detected from all amplifiers of the group of amplifiers match expected data.

15. The method of claim 14 , wherein the identifying the sub-group comprises:
applying the re-offset voltage to compensation transistors of the group of amplifiers.

16. The method of claim 14 , wherein the identifying the sub-group comprises testing each amplifier of the group of amplifiers using a built-in self-test (BIST) circuit.

17. The method of claim 14 , wherein the identifying the sub-group comprises applying the re-offset voltage to a bulk of a compensation transistor of the group of amplifiers.

18. The method of claim 14 , wherein the setting the re-offset voltage comprises sequentially decreasing or sequentially increasing the re-offset voltage.

19. The method of claim 18 , further comprising setting the re-offset voltage as a desired re-offset voltage for a compensation transistor of an amplifier of the group of amplifiers if the results match the expected data.

20. The method of claim 14 , wherein the setting the re-offset voltage comprises setting the re-offset voltage using a binary search technique.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Upputuri Bharath
• Sampigethaya Shreekanth

Classifications

• G11C29/02

  Detection or location of defective auxiliary circuits, e.g. defective refresh counters · CPC title

• H03F3/45179

  using MOSFET transistors as the active amplifying circuit (H03F3/45278 takes precedence) · CPC title

• H03F2200/471

  the voltage being sensed · CPC title

• G11C29/12

  Built-in arrangements for testing, e.g. built-in self testing [BIST] {or interconnection details} · CPC title

• G11C7/065 Primary

  Differential amplifiers of latching type · CPC title