Class-D amplifier having mixed signal feedback control

Patent metadata

Field	Value
Publication number	US-9319011-B2
Application number	US-201414300803-A
Country	US
Kind code	B2
Filing date	Jun 10, 2014
Priority date	Apr 21, 2014
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

A Class-D amplifier includes an analog-to-digital converter (ADC), a digital filter, a digital pulse width modulation (PWM) unit, a pre-driver unit, and an output driver. The ADC is configured to receive an input signal and one or more feedback signals, and to generate a first digital signal. The digital filter, the digital PWM unit, and the pre-driver unit are configured to generate control signals based on the first digital signal. The output driver is configured to generate an output signal based on the control signals. A first feedback path is defined as from a first output node of the output driver to a first input node of the ADC; and a second feedback path is defined as from a second output node of the output driver to a second input node of the ADC. The first and second feedback paths are free from a low-pass filtering device.

First claim

What is claimed is:

1. A Class-D amplifier, comprising:
an analog-to-digital converter (ADC) having a first input node, the ADC being configured to:
receive a first analog input signal and a first feedback signal at the first input node of the ADC, and
generate a first digital signal based on the first analog input signal and the first feedback signal;

a digital filter configured to generate a second digital signal based on the first digital signal;
a digital pulse width modulation (PWM) unit configured to generate a first PWM signal based on the second digital signal;
a first pre-driver unit configured to generate a first set of control signals based on the first PWM signal;
a first output driver having an output node, the first output driver being configured to generate a first output signal at the output node of the first output driver based on the first set of control signals; and
a first feedback unit configured to generate the first feedback signal based on the first output signal, a first feedback path being defined as from the output node of the first output driver through the first feedback unit to the first input node of the ADC, and the first feedback path being free from a low-pass filtering device that has a cutoff frequency lower than a sampling frequency of the ADC.

2. The Class-D amplifier of claim 1 , wherein the ADC, the digital filter, the first pre-driver unit, and the first feedback unit are configured in a manner that the first feedback path functions as a negative feedback path with respect to the first analog input signal.

3. The Class-D amplifier of claim 1 , wherein the first feedback unit comprises a resistive network configured as a voltage divider.

4. The Class-D amplifier of claim 1 , wherein the ADC is a continuous-time ADC.

5. The Class-D amplifier of claim 1 , wherein
the first analog input signal has a signal bandwidth ranging from a zero frequency to a predetermined frequency; and
the sampling frequency of the ADC is not less than a predetermined multiple of the predetermined frequency, the predetermined multiple being at least 2.

6. The Class-D amplifier of claim 5 , wherein the predetermined multiple is 64, 128, or 256.

7. The Class-D amplifier of claim 1 , wherein the digital filter comprises a loop filter followed by a compensation filter.

8. The Class-D amplifier of claim 1 , wherein
the ADC further comprises a second input node, and the ADC is further configured to:
receive a second analog input signal and a second feedback signal at the second input node of the ADC, and
generate the first digital signal based on the first analog input signal, the first feedback signal, the second analog input signal, and the second feedback signal;

the digital PWM unit is further configured to generate a second PWM signal based on the second digital signal; and
the Class-D amplifier further comprises:
a second pre-driver unit configured to generate a second set of control signals based on the second PWM signal;
a second output driver having an output node, the second output driver being configured to generate a second output signal at the output node of the second output driver based on the second set of control signals; and
a second feedback unit configured to generate the second feedback signal based on the second output signal, a second feedback path being defined as from the output node of the second output driver through the second feedback unit to the second input node of the ADC, and the second feedback path being free from a low-pass filtering device that has a cutoff frequency lower than the sampling frequency of the ADC.

9. The Class-D amplifier of claim 8 , wherein the ADC, the digital filter, the second pre-driver unit, and the second feedback unit are configured in a manner that the second feedback path functions as a negative feedback path with respect to the second analog input signal.

10. The Class-D amplifier of claim 8 , wherein the second feedback unit comprises a resistive network configured as a voltage divider.

11. The Class-D amplifier of claim 8 , wherein the ADC is a delta-sigma continuous-time ADC.

12. The Class-D amplifier of claim 11 , wherein the ADC comprises:
a first integration stage comprising input nodes and output nodes, the input nodes of the first integration stage being coupled with the first input node and the second input node of the ADC;
a second integration stage comprising input nodes and output nodes, the input nodes of the second integration stage being coupled with the output nodes of the first integration stage;
a quantizer comprising input nodes and one or more output nodes, the input nodes of the quantizer being coupled with the output nodes of the second integration stage, and the one or more output nodes being configured to carry the first digital signal; and
one or more digital-to-analog converters (DACs) configured to generate feedback signals at input nodes of the first integration stage and the input nodes of the second integration stage based on the first digital signal.

13. The Class-D amplifier of claim 12 , wherein the one or more DACs comprise a current-steering type DAC, and the current-steering type DAC comprises:
a first output node;
a second output node;
a control unit configured to generate a third set of control signals based on the first digital signal; and
a current cell comprising:
a first current source configured to inject a first current to the first output node of the current-steering type DAC or the second output node of the current-steering type DAC;
a second current source configured to extract a second current from the first output node of the current-steering type DAC or the second output node of the current-steering type DAC; and
a set of switches configured to selectively electrically couple the first current source or the second current source with the first output node of the current-steering type DAC or the second output node of the current-steering type DAC according to the third set of control signals.

14. A circuit, comprising:
an analog-to-digital converter (ADC) having a non-inverted input node, an inverted input node, and an N-bit digital output port, N being a positive integer;
a digital filter having an input port and an output port, the input port of the digital filter being coupled to the output port of the ADC;
a digital pulse width modulation (PWM) unit having an input port, a first PWM output node, and a second PWM output node, the input port of the digital PWM unit being coupled to the output port of the digital filter;
a first pre-driver unit comprising an input node, a first output node, and a second output node, the input node of the first pre-driver unit being coupled to the first PWM output node;
a first Class-D output driver having a first input node, a second input node, and an output node, the first input node of the first Class-D output driver being coupled to the first output node of the first pre-driver unit, the second input node of the first Class-D output driver being coupled to the second output node of the first pre-driver unit;
a first resistive network having a first node and a second node, the first node of the first resistive network coupled to the output node of the first Class-D output driver, and the second node of the first resistive network coupled to the non-inverted input node of the ADC, a first feedback path being defined as from the output node of the first Class-D output driver through the first resistive network to the non-inverted input node of the ADC, and the first feedback path being free from a low-pass filtering device that has a cuto

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Kinyua Martin
• Soenen Eric

Classifications

• H03F3/217 Primary

  Class D power amplifiers; Switching amplifiers · CPC title

• H03F2200/03

  the amplifier being designed for audio applications · CPC title

• H03M1/12

  Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03F3/183

  with semiconductor devices only · CPC title

• H03M1/747

  with equal currents which are switched by unary decoded digital signals · CPC title