Metal deposition on substrates

Patent metadata

Field	Value
Publication number	US-9318446-B2
Application number	US-201414185272-A
Country	US
Kind code	B2
Filing date	Feb 20, 2014
Priority date	Mar 15, 2013
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

Various techniques, methods, devices and apparatus are provided where an isolation layer is provided at a peripheral region of the substrate, and one or more metal layers are deposited onto the substrate.

First claim

What is claimed is:

1. A method comprising:
providing a semiconductor wafer;
forming an isolation layer over the semiconductor wafer, the isolation layer being substantially limited to a peripheral region of the semiconductor wafer; and
forming at least one first metal layer over a side of the semiconductor wafer.

2. The method of claim 1 , wherein the isolation layer is formed after forming the first metal layer.

3. The method of claim 1 , wherein the first metal layer is formed after forming the isolation layer.

4. The method of claim 1 , wherein forming the isolation layer comprises forming the isolation layer within the peripheral region and outside the peripheral region, and removing the isolation layer from outside the peripheral region.

5. The method of claim 1 , wherein forming the isolation layer comprises performing a photolithography.

6. The method of claim 1 , further comprising forming at least one second metal layer after forming the first metal layer and after forming the isolation layer.

7. The method of claim 6 , wherein the second metal layer comprises nickel.

8. The method of claim 7 , wherein the nickel is in the form of at least one of pure nickel, nickel alloy, or nickel compound.

9. The method of claim 1 , wherein the forming the first metal layer includes electroless plating the first metal layer.

10. The method of claim 1 , wherein the peripheral region comprises at least one of a peripheral portion of the side of the semiconductor wafer or at least a portion of an edge of the semiconductor wafer.

11. A device comprising:
a semiconductor wafer;
an isolation layer substantially limited to a peripheral region of the semiconductor wafer; and
a metal layer over a side of the semiconductor wafer, the metal layer being at least partially adjacent the isolation layer.

12. The device of claim 11 , wherein the isolation layer comprises at least one of a nitride or an oxide.

13. The device of claim 11 , wherein the side is a backside of the semiconductor wafer, wherein devices are formed over a front side of the semiconductor wafer.

14. The device of claim 11 , wherein the isolation layer is between the semiconductor wafer and the metal layer.

15. The device of claim 11 , wherein the metal layer is between the semiconductor wafer and the isolation layer.

16. The device of claim 11 , wherein the peripheral region comprises at least one of a peripheral portion of the side of the semiconductor wafer or at least a portion of an edge of the semiconductor wafer.

17. A method comprising:
providing a substrate comprising a thinned semiconductor substrate with a ring thicker than the thinned semiconductor substrate at a peripheral region;
forming an isolation layer over the substrate, the isolation layer being substantially limited to the peripheral region of the substrate; and
forming at least one first metal layer over a side of the substrate.

18. A device comprising:
a substrate comprising a center region and a ring provided in a peripheral region, the ring being thicker than the center region;
an isolation layer substantially limited to the peripheral region of the substrate, wherein the isolation layer at least partially covers the ring; and
a metal layer over a side of the substrate, the metal layer being at least partially adjacent the isolation layer.

19. The device of claim 18 , wherein the center region has a thickness below 100 μm.

Assignees

• Infineon Technologies Austria

Inventors

• Wang Kae-Horng
• Santos Rodriguez Francisco Javier
• Knabl Michael
• Koffler Guenther

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1906

  Preparing SOI wafers · CPC title

• H10P90/18

  by shaping · CPC title

• H10P72/0476

  comprising at least one plating chamber · CPC title

• H10P72/0474

  comprising at least one lithography chamber · CPC title