Interconnect structure and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9318439-B2
Application number	US-201414222181-A
Country	US
Kind code	B2
Filing date	Mar 21, 2014
Priority date	Mar 21, 2014
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

The present disclosure provides an interconnect structure, including a substrate, a first conductive feature over the substrate, a second conductive feature over the first conductive feature, and a dielectric layer surrounding the first conductive feature and the second conductive feature. A width of the first conductive feature and a width of the second conductive feature are between 10 nm and 50 nm. The present disclosure also provides a method for manufacturing an interconnect structure, including (1) forming a via opening and a line trench in a dielectric layer, (2) forming a 1-dimensional conductive feature in the via opening, (3) forming a conformal catalyst layer over a sidewall of the line trench, a bottom of the line trench, and a top of the 1-dimensional conductive feature, and (4) removing the conformal catalyst layer from the bottom of the line trench and the top of the 1-dimensional conductive feature.

First claim

What is claimed is:

1. An interconnect structure, comprising:
a substrate;
a first conductive feature, comprising materials of 1-dimensional conduction feature, and forming a continuous region over the substrate;
a second conductive feature over the first conductive feature, comprising materials of 2-dimensional conduction feature; and
a third conductive feature under the 1-dimensional conduction feature;
a dielectric layer surrounding the first conductive feature and the second conductive feature,
wherein a width of the first conductive feature and a width of the second conductive feature are in a range of from about 10 nm to about 50 nm.

2. The interconnect structure of claim 1 , wherein the third conductive feature is electrically connected with the first conductive feature.

3. The interconnect structure of claim 2 , wherein the third conductive feature comprises a source region, a drain region, a gate region, a conductive via, a conductive line, or a contact region.

4. The interconnect structure of claim 1 , wherein the first conductive feature comprises a carbon nanotube (CNT).

5. The interconnect structure of claim 1 , wherein the second conductive feature comprises a graphene sheet.

6. The interconnect structure of claim 1 , further comprising a first catalyst layer at an interface between the second conductive feature and the dielectric layer.

7. The interconnect structure of claim 6 , wherein a thickness of the catalyst layer is in a range of from about 0.5 nm to about 2 nm.

8. The interconnect structure of claim 6 , further comprising a second catalyst layer at an interface between the first conductive feature and the third conductive feature.

9. The interconnect structure of claim 6 , wherein the 2-dimensional conduction feature of the second conductive feature comprises a structure conducting electrons on a surface parallel to the interface between the second conductive feature and the dielectric layer.

10. The interconnect structure of claim 6 , further comprising a barrier layer between the first catalyst layer and the dielectric layer.

11. An integrated circuit structure, comprising:
a substrate;
a 1-dimensional conductive feature comprising a carbon nanotube over the substrate;
a first dielectric layer surrounding the 1-dimensional conductive feature;
a 2-dimensional conductive feature comprising a graphene sheet over the substrate;
a second dielectric layer surrounding the 2-dimensional conductive feature, and
a catalyst layer of the graphene sheet between the 2-dimensional conductive feature and the second dielectric layer, the catalyst layer being free from over a top surface of the 1-dimensional conductive feature,
wherein an aspect ratio of the 1-dimensional conductive feature and an aspect ratio of the 2-dimensional conductive feature are in a range of from about 4 to about 10.

12. The integrated circuit structure of claim 11 , further comprising an etch stop layer between the substrate and the first dielectric layer.

13. The integrated circuit structure of claim 11 , further comprising a barrier layer between the 1-dimensional conductive feature and the first dielectric layer.

14. The semiconductor device of claim 1 , wherein an aspect ratio of the first conductive feature and an aspect ratio of the second conductive feature are in a range of from about 4 to about 10.

15. The semiconductor device of claim 6 , wherein the first catalyst layer comprises transitional metal.

16. The semiconductor device of claim 8 , wherein the second catalyst layer comprises silicide.

17. The semiconductor device of claim 8 , wherein a thickness of the second catalyst layer is greater than a thickness of the first catalyst layer.

18. The semiconductor device of claim 11 , further comprising a transistor under the 1-dimensional conductive feature and the 2-dimensional conductive feature, electrically connected with the first conductive feature.

19. The semiconductor device of claim 11 , wherein a thickness of the catalyst layer is in a range of from about 0.5 nm to about 2 nm.

20. An interconnect structure, comprising:
a substrate;
a first conductive feature over the substrate, comprising materials of 1-dimensional conduction feature;
a second conductive feature, comprising materials of 2-dimensional conduction feature, and forming a continuous region over the first conductive feature; and
a dielectric layer surrounding the first conductive feature and the second conductive feature.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Yang Shin-Yi
• Tien Hsi-Wen
• Lee Ming-Han
• Lee Hsiang-Huan
• Shue Shau-Lin

Classifications

• H10P14/43

  Chemical deposition, e.g. chemical vapour deposition [CVD] · CPC title

• H10P14/432

  using selective deposition · CPC title

• H10W20/0554

  of nanotubes or nanowires · CPC title

• H10W20/4462

  Carbon or carbon-containing materials, e.g. graphene · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title