Instruction set architecture mode dependent sub-size access of register with associated status indication

Patent metadata

Field	Value
Publication number	US-9317285-B2
Application number	US-201213460178-A
Country	US
Kind code	B2
Filing date	Apr 30, 2012
Priority date	Apr 30, 2012
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

A system and method for efficiently reducing the power consumption of register file accesses. A processor is operable to execute instructions with two or more data types, each with an associated size and alignment. Data operands for a first data type use operand sizes equal to an entire width of a physical register within a physical register file. Data operands for a second data type use operand sizes less than an entire width of a physical register. Accesses of the physical register file for operands associated with a non-full-width data type do not access a full width of the physical registers. A given numerical value may be bypassed for the portion of the physical register that is not accessed.

First claim

What is claimed is:

1. A processor comprising:
a physical register file comprising a plurality of physical registers configured to store data associated with a plurality of data types corresponding to at least two different sizes; and
control circuitry;
wherein the control circuitry is configured to:
store an indication of a mode of at least two modes in a register;
access said register to detect the mode of at least two modes that indicates whether instructions corresponding to a first instruction set architecture (ISA) are being processed or instructions corresponding to a second ISA different from the first ISA are being processed, wherein the first ISA does not support data operands with a size equal to a full size of a register of the plurality of registers and the second ISA does support data operands with a size equal to the full size of a register of the plurality of registers;
in response to detecting a first mode of the at least two modes, determine a first instruction is associated with the first ISA, allow access to a first portion of a given register of the plurality of physical registers identified by the first instruction and prevent access to a second portion of the given register;
in response to detecting a second mode of the at least two modes, determine the first instruction is associated with the second ISA and allow access to the full size of the given register; and
in response to detecting the first mode and the given register is a destination register for the first instruction, store a first indication corresponding to the given register that indicates the given register is being used to store a data operand associated with the first ISA.

2. The processor as recited in claim 1 , wherein in response to detecting the second mode and the given register is a destination register for the first instruction, the control circuitry is further configured to store a second indication corresponding to the given register which indicates the given register is being used to store a data operand associated with the second ISA.

3. The processor as recited in claim 1 , wherein to detect whether the first instruction is associated with the first mode or the second mode, the control circuitry is further configured to access a link register storing a return address used after a call in program code, wherein an indication of the first mode or the second mode is included in the return address.

4. The processor as recited in claim 1 , wherein in response to detecting a read of the given register while in the second mode for a source operand with a size greater than the first portion, the control circuitry is further configured to return both a data operand stored in the first portion of the given register and a predetermined value for a portion of the given register not used to store the data operand.

5. The processor as recited in claim 4 , wherein the predetermined value is one or more bits set equal to zero.

6. The processor as recited in claim 2 , wherein the processor further comprises a reservation station configured to store the first indication and the second indication.

7. The processor as recited in claim 1 , wherein when the first instruction corresponds to the first ISA, the data operand has a size equal to half the given register.

8. A method comprising:
storing data associated with a plurality of data types in a physical register file comprising a plurality of physical registers, said data types corresponding to at least two different sizes;
storing an indication of a mode of at least two modes in a register;
accessing said register to detect the mode of at least two modes that indicates whether instructions corresponding to a first instruction set architecture (ISA) are being processed or instructions corresponding to a second ISA different from the first ISA are being processed, wherein the first ISA does not support data operands with a size equal to a full size of a register of the plurality of registers and the second ISA does support data operands with a size equal to the full size of a register of the plurality of registers;
in response to detecting a first mode of the at least two modes, determining a first instruction is associated with the first ISA, allowing access to a first portion of a given register of the plurality of physical registers identified by the first instruction and preventing access to a second portion of the given register;
in response to detecting a second mode of the at least two modes, determining the first instruction is associated with the second ISA and allowing access to the full size of the given register; and
in response to detecting the first mode and the given register is a destination register for the first instruction, storing a first indication corresponding to the given register that indicates the given register is being used to store a data operand associated with the first ISA.

9. The method as recited in claim 8 , wherein in response to detecting the second mode and the given register is a destination register for the first instruction, the method further comprises storing a second indication corresponding to the given register which indicates the given register is being used to store a data operand associated with the second ISA.

10. The method as recited in claim 8 , wherein detecting whether the first instruction is associated with the first mode or the second mode comprises accessing a link register storing a return address used after a call in program code, wherein an indication of the first mode or the second mode is included in the return address.

11. The method as recited in claim 8 , wherein in response to detecting a read of the given register for a source operand with a size greater than the data operand stored in the given register, the method comprises returning both the data operand and a predetermined value for a portion of the given register not used to store the data operand.

12. The method as recited in claim 11 , the predetermined value is one or more bits set equal to zero.

13. The method as recited in claim 8 , wherein the first portion is half of the given one of the plurality of physical registers.

14. A physical register file comprising:
an array comprising a plurality of physical registers;
an interface configured to receive array access requests; and
access control logic; and
wherein the access control logic is configured to:
store an indication of a mode of at least two modes in a register;
access said register to detect whether an instruction accessing the register file in a given clock cycle is associated with a first mode of the at least two modes rather than a second mode different from the first mode, wherein the first mode corresponds to a first instruction set architecture (ISA) that does not support data operands with a size equal to a full size of a register of the plurality of registers and the second ISA does support data operands with a size equal to the full size of a register of the plurality of registers;
in response to detecting each instruction accessing the register file in the given clock cycle is associated with the first mode, prevent access to a first portion in each register of the plurality of physical registers; and
in response to detecting each instruction accessing the register file in the given clock cycle is associated with the second mode, allow access a full register of each register of the plurality of physical registers; and
in response to detecting each instruction accessing the register file in the given clock cycle is associated with the first mode, store a first indication corresponding to destination

Assignees

• Gupta Sandeep
• Blasco-Allue Conrado
• Mylius John H
• Williams Iii Gerard R
• Keller James B
• Apple Inc

Inventors

• Gupta Sandeep
• Blasco-Allue Conrado
• Mylius John H
• Williams Iii Gerard R
• Keller James B

Classifications

• G06F1/3234

  Power saving characterised by the action undertaken · CPC title

• G06F9/30141 Primary

  Implementation provisions of register files, e.g. ports · CPC title

• G06F9/384

  Register renaming · CPC title

• G06F9/30112

  comprising data of variable length · CPC title