Register file having a plurality of sub-register files

US9304934B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9304934-B2
Application numberUS-201414157805-A
CountryUS
Kind codeB2
Filing dateJan 17, 2014
Priority dateJan 24, 2013
Publication dateApr 5, 2016
Grant dateApr 5, 2016

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Abstract

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Register files for use in an out-of-order processor that have been divided into a plurality of sub-register files. The register files also have a plurality of buffers which are each associated with one of the sub-register files. Each buffer receives and stores write operations destined for the associated sub-register file which can be later issued to the sub-register file. Specifically, each clock cycle it is determined whether there is at least one write operation in the buffer that has not been issued to the associated sub-register file. If there is at least one write operation in the buffer that has not been issued to the associated sub-register file, one of the non-issued write operations is issued to the associated sub-register file. Each sub-register file may also have an arbitration logic unit which resolves conflicts between read and write operations that want to access the associated sub-register file in the same cycle by prioritizing read operations unless a conflicting write instruction has reached commit time.

First claim

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The invention claimed is: 1. A register file for use in an out-of-order processor, the register file comprising: a plurality of sub-register files, each sub-register file comprising at least one physical register; and a plurality of buffers, each buffer being associated with a sub-register file and arranged to: receive write operations destined for the associated sub-register file; store each received write operation in the buffer; receive a write value for each write opera…

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What does patent US9304934B2 cover?
Register files for use in an out-of-order processor that have been divided into a plurality of sub-register files. The register files also have a plurality of buffers which are each associated with one of the sub-register files. Each buffer receives and stores write operations destined for the associated sub-register file which can be later issued to the sub-register file. Specifically, each cl…
Who is the assignee on this patent?
Imagination Tech Ltd, Imagination Tech Ltd
What technology area does this patent fall under?
Primary CPC classification G06F9/3012. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Apr 05 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).