Semiconductor device, detection method and program

Patent metadata

Field	Value
Publication number	US-9316684-B2
Application number	US-201113635057-A
Country	US
Kind code	B2
Filing date	Mar 14, 2011
Priority date	Mar 15, 2010
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

A semiconductor device and the like that can determine the performance of a semiconductor integrated circuit with higher accuracy even when test environment fluctuates. The semiconductor device detects degradation of the semiconductor integrated circuit, including measurement unit that measures temperature and voltage, decision unit that judges whether the test is executed within an allowable test timing in the detection target circuit portion at each test operation frequency and decides a maximum test operation frequency and calculation unit that converts a maximum test operation frequency into that at a standard temperature and voltage and calculates a degradation amount. The semiconductor integrated circuit has a monitor block circuit that monitors the values for the measurement unit to measure temperature and voltage. The measurement unit has estimation unit that estimates temperature and voltage of a detection target circuit portion based on the monitored values. The calculation unit uses the estimated temperature and voltage.

First claim

The invention claimed is:

1. A semiconductor device for detecting degradation which occurs in a semiconductor integrated circuit having a detection target circuit portion where a test is executed, comprising:
a decision unit that judges whether the test is executed within an allowable test timing in the detection target circuit portion at each test operation frequency or not and decides a maximum test operation frequency at which the test can be executed;
a measurement unit that measures variables indicating test environment, the variables being a temperature and a voltage of where the detection target circuit portion is; and
a calculation unit that converts the maximum test operation frequency decided by the decision unit based on the temperature and the voltage measured by the measurement unit into a maximum test operation frequency at a standard temperature and a standard voltage, and calculates, based on a converted maximum test operation frequency, a degradation amount which indicates degree of degradation;
wherein the semiconductor integrated circuit has a monitor block circuit that monitors a value used by the measurement unit to measure the temperature and the voltage;
the measurement unit has an estimation unit that estimates a temperature and a voltage of where the detection target circuit portion is, every time a test is executed, based on a monitored value by the monitor block circuit which operated at a temperature and a voltage of where the detection target circuit portion is;
the calculation unit uses the temperature and the voltage estimated by the estimation unit as the temperature and the voltage measured by the measurement unit and converts the maximum test operation frequency decided by the decision unit into the maximum test operation frequency at the standard temperature and the standard voltage;
the semiconductor device further comprises n (n is an integer equal to or more than 2) of the monitor block circuits;
the measurement unit measures a measured frequency F i (i is an integer equal to or less than n) obtained as an oscillation number of times at each monitor block circuit within a predetermined time; and
the estimation unit estimates the temperature T and the voltage V of where the detection target circuit portion is by calculating coefficients α i , β, α′ i , and β′ in an equation (eq1):

T
=

∑

i
=
1

n

⁢

α
i

⁢

F
i

+
β

,

⁢

V
=

∑

i
=
1

n

⁢

α
i
′

⁢

F
i

+

β
′

.

(

eq
⁢

⁢
1

)

2. The semiconductor integrated circuit of claim 1 ,
wherein the estimation unit estimates the temperature T and the voltage V of where the detection target circuit portion is by dividing a temperature range or a voltage range into pluralities of divisions and calculating the coefficients α i , β, α′ i , and β′ in an equation (eq1) for each of the divisions, or by dividing a temperature range into pluralities of divisions and calculating the coefficients α i , and β in an equation (eq1) for each of the divisions with dividing a voltage range into pluralities of divisions and calculating the coefficients α′ i , and β′ in an equation (eq1) for each of the divisions.

3. The semiconductor integrated circuit of claim 1 ,
wherein the estimation unit estimates the temperature T and the voltage V of where the detection target circuit portion is by using a frequency difference ΔF i which is a difference between the measured frequency F i and a first measured frequency F i0 , instead of using the measured frequency F i .

4. The semiconductor integrated circuit of claim 1 , further comprising a storing unit that stores a combination of measured values measured by the measurement unit and a maximum test operation frequency decided by the decision unit,
wherein the calculation unit uses measured values and a maximum test operation frequency stored by the storing unit.

5. The semiconductor integrated circuit of claim 4 ,
wherein the maximum test operation frequency is decided through calculation to remove random noise based on pluralities of maximum test operation frequencies stored by the storing unit at different tests.

6. The semiconductor integrated circuit of claim 1 ,
wherein the measurement unit measures an initial temperature and an initial voltage in a test at a predetermined test operation frequency; and
the decision unit decides a maximum test operation frequency candidate at the initial temperature and the initial voltage using the standard temperature, the standard voltage and a maximum test operation frequency at a previous time, and decides, by decreasing a frequency after increasing or by only increasing or only decreasing a frequency, a maximum test operation frequency at which the test can be executed.

7. The semiconductor integrated circuit of claim 1 ,
wherein tests are prepared for each of different lengths of paths to be tested.

8. The semiconductor integrated circuit of claim 1 ,
wherein the test or an order of the test is modifiable according to an allowable test timing and/or the degradation amount.

9. A semiconductor device for detecting variability which occurs in pluralities of same kinds of semiconductor integrated circuits where a test is executed, comprising:
a

Assignees

• Sato Yasuo
• Kajihara Seiji
• Inoue Michiko
• Yoneda Tomokazu
• Yi Hyunbean
• Miura Yukiya
• Kyushu Inst Technology
• Nat Univ Corp Nara Inst
• Univ Tokyo Metropolitan

Inventors

• Sato Yasuo
• Kajihara Seiji
• Inoue Michiko
• Yoneda Tomokazu
• Yi Hyunbean
• Miura Yukiya

Classifications

• G01R31/2884 Primary

  using dedicated test connectors, test elements or test circuits on the IC under test (G01R31/2855 takes precedence) · CPC title

• G01R31/3016

  Delay or race condition test, e.g. race hazard test · CPC title

• G01R19/252

  using analogue/digital converters of the type with conversion of voltage or current into frequency and measuring of this frequency · CPC title

• G01R31/2882

  Testing timing characteristics · CPC title

• G01R31/2879

  related to electrical aspects, e.g. to voltage or current supply or stimuli or to electrical loads · CPC title