Semiconductor devices, methods of manufacturing thereof, and image sensor devices

Patent metadata

Field	Value
Publication number	US-9312294-B2
Application number	US-201314063953-A
Country	US
Kind code	B2
Filing date	Oct 25, 2013
Priority date	Oct 25, 2013
Publication date	Apr 12, 2016
Grant date	Apr 12, 2016

Abstract

Semiconductor devices, methods of manufacturing thereof, and image sensor devices are disclosed. In some embodiments, a semiconductor device comprises a semiconductor chip comprising an array region, a periphery region, and a through-via disposed therein. The semiconductor device comprises a guard structure disposed in the semiconductor chip between the array region and the through-via or between the through-via and a portion of the periphery region.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor chip comprising an array region, a periphery region, and a through-via disposed in the semiconductor chip; and
a guard structure disposed in the semiconductor chip between the array region and the through-via or between the through-via and a portion of the periphery region, the guard structure comprising a metal feature, a p-type region, and an n-type region, wherein a first insulating material is on sidewalls of the metal feature and a second insulating material is adjacent the p-type region and the n-type region.

2. The semiconductor device according to claim 1 , wherein the semiconductor chip comprises a first semiconductor chip, wherein the semiconductor device further comprises a second semiconductor chip bonded to the first semiconductor chip, and wherein the through-via is also disposed within the second semiconductor chip.

3. The semiconductor device according to claim 2 , wherein the semiconductor device further comprises a third semiconductor chip bonded to the second semiconductor chip, and wherein the through-via is also disposed within the third semiconductor chip.

4. The semiconductor device according to claim 3 , further comprising:
a second through-via disposed in the first semiconductor chip and extending from the first semiconductor chip into the second semiconductor chip, wherein the second through-via does not extend into the third semiconductor chip; and
a third through-via disposed in the first semiconductor chip, wherein the third through-via does not extend into the second semiconductor chip or the third semiconductor chip.

5. The semiconductor device according to claim 1 , wherein the guard structure comprises a first guard structure, wherein the first guard structure is disposed in the semiconductor chip between the array region and the through-via, and wherein the semiconductor device further comprises a second guard structure disposed in the semiconductor chip between the through-via and the portion of the periphery region.

6. The semiconductor device according to claim 1 , wherein the periphery region is disposed around the array region.

7. The semiconductor device according to claim 1 , wherein the array region comprises an array of pixels.

8. The semiconductor device according to claim 1 , wherein the semiconductor chip comprises a plurality of the through-vias; wherein the semiconductor chip comprises a plurality of periphery devices in the periphery region; and wherein the guard structure is disposed proximate or around the array region, disposed proximate or around the plurality of through-vias, disposed proximate or around the plurality of through-vias and the array region, disposed proximate or around one of the plurality of through-vias, disposed proximate or around a group of the plurality of through-vias, disposed proximate or around one of the plurality of periphery devices, disposed proximate or around a group of the plurality of periphery devices, or a combination thereof.

9. The semiconductor device according to claim 1 , wherein the first insulating material has a thickness of about 1 nm to about 20 μm on the sidewalls of the metal feature.

10. A method of manufacturing a semiconductor device, the method comprising:
providing a semiconductor chip comprising an array region, a periphery region, and a through-via disposed therein; and
forming a guard structure in the semiconductor chip between the array region and the through-via or between the through-via and a portion of the periphery region, wherein forming the guard structure comprises:
forming a trench in a first portion of the semiconductor chip;
filling the trench with a conductive material;
implanting a second portion of the semiconductor chip with an n-type impurity to form an n-type region;
implanting a third portion of the semiconductor chip with a p-type impurity to form a p-type region; and
forming shallow trench isolation regions in the semiconductor chip proximate the n-type region and the p-type region, the shallow trench isolation regions comprising an insulating material.

11. The method according to claim 10 , wherein the guard structure is formed at a depth of about 0.01 μm to about 100 μm below a surface of the semiconductor chip.

12. The method according to claim 10 , wherein the guard structure has a width of about 0.01 μm or greater.

13. The method according to claim 10 , wherein the guard structure is spaced apart from the through-via by about 0.1 μm or greater.

14. The method according to claim 10 , wherein filling the trench with the conductive material comprises filling the trench with a material selected from the group consisting essentially of: W, Cu, AlCu, and combinations thereof.

15. The method according to claim 10 , wherein forming the trench of the guard structure comprises a lithography process.

16. The method according to claim 10 , further comprising applying a voltage to the guard structure, wherein applying the voltage improves noise reduction of the guard structure.

17. An image sensor device, comprising:
a first semiconductor chip comprising an array region, a periphery region disposed around the array region, and a first through-via disposed between the array region and the periphery region;
a second semiconductor chip bonded to the first semiconductor chip, the second semiconductor chip comprising a second through-via disposed therein, the second through-via also being disposed in the first semiconductor chip; and
a guard structure disposed in the first semiconductor chip between the array region and the first through-via or the second through-via, or between a portion of the periphery region and the first through-via or the second through-via.

18. The device according to claim 17 , wherein the guard structure comprises a metal feature and wherein a voltage of about −10 Volts (V) to about 10 V is applicable to the metal feature during operation of the image sensor device; wherein the guard structure comprises a P-type region and wherein a voltage of about 0 V to about −10 V is applicable to the P-type region during the operation of the image sensor device; or wherein the guard structure comprises an N-type region and wherein a voltage of about 0.1 V to about 10 V is applicable to the N-type region during the operation of the image sensor device.

19. The device according to claim 17 , wherein the image sensor device comprises a stacked complementary metal oxide semiconductor (CMOS) back side illumination (BSI) image sensor device.

20. The device according to claim 17 , wherein:
the guard structure comprises a metal feature;
a voltage is applied to the metal feature during operation of the image sensor device; and
application of the voltage improves noise reduction of the guard structure.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Chuang Chun-Chieh
• Yaung Dun-Nian
• Liu Jen-Cheng
• Hsu Tzu-Hsuan
• Hung Feng-Chi
• Kao Min-Feng

Classifications

• H10F39/809

  of hybrid image sensors · CPC title

• H10F39/807

  Pixel isolation structures · CPC title

• H10F39/802

  Geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes · CPC title

• H10F39/199

  Back-illuminated image sensors · CPC title

• H10F39/026

  Wafer-level processing · CPC title