Integrated circuits and manufacturing methods thereof

Patent metadata

Field	Value
Publication number	US-9312260-B2
Application number	US-201113086186-A
Country	US
Kind code	B2
Filing date	Apr 13, 2011
Priority date	May 26, 2010
Publication date	Apr 12, 2016
Grant date	Apr 12, 2016

Abstract

An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.

First claim

What is claimed is:

1. An integrated circuit comprising:
a first diffusion area for a first type transistor, the first type transistor including a first drain region and a first source region in the first diffusion area;
a second diffusion area for a second type transistor, the second diffusion area being separated from the first diffusion area, the second type transistor including a second drain region and a second source region in the second diffusion area;
a gate electrode continuously extending across the first diffusion area and the second diffusion area in a routing direction;
a first metallic structure comprising at least one first metal, the first metallic structure overlaps the first diffusion area in the routing direction and is electrically coupled with the first drain region;
a second metallic structure comprising the at least one first metal, the second metallic structure overlaps the second diffusion area in the routing direction and is electrically coupled with the second drain region; and
a third metallic structure comprising at least one second metal different from the first metal, the third metallic structure having side surfaces,
wherein
the third metallic structure is over the first metallic structure, a portion of the third metallic structure that is over the first metallic structure has a substantially planar bottom surface in direct physical contact a substantially planar top surface of with the first metallic structure,

the third metallic structure is over the second metallic structure, a portion of the third metallic structure that is over the second metallic structure has a substantially planar bottom surface in direct physical contact a substantially planar top surface of with the second metallic structure,
the side surfaces of the third metallic structure are between the first metallic structure and the second metallic structure,
the side surfaces of the third metallic structure are in direct physical contact with the first metallic structure and the second metallic structure, and

a width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.

2. The integrated circuit of claim 1 , wherein a ratio of the width of the first metallic structure to the width of the third metallic structure ranges from about 1:1 to about 2:1.

3. The integrated circuit of claim 2 , wherein a ratio of the width of the first metallic structure to the width of the third metallic structure ranges from about 1.3:1 to about 1.6:1.

4. The integrated circuit of claim 1 , wherein the first and second metallic structures substantially continuously extend, in the routing direction, from an edge to an opposite edge of the first and second diffusion areas, respectively.

5. The integrated circuit of claim 1 , further comprising:
a fourth metallic structure electrically coupled with the first source region; and
a fifth metallic structure over and electrically coupled with the fourth metallic structure,
wherein the fifth metallic structure and the first diffusion area overlap by a first distance in the routing direction, the third metallic structure and the first diffusion area overlap by a second distance in the routing direction, and the first distance is larger than the second distance.

6. The integrated circuit of claim 5 , wherein the first diffusion area has a first width, a ratio of the first distance to the first width ranges from about 0.75:1 to about 1:1 and a ratio of the second distance to the first width ranges from about 0.1:1 to about 0.33:1.

7. The integrated circuit of claim 5 , wherein a ratio of a width of the fourth metallic structure to a width of the fifth metallic structure ranges from about 1:1 to about 2:1.

8. The integrated circuit of claim 7 , wherein a ratio of the width of the fourth metallic structure to the width of the fifth metallic structure ranges from about 1.3:1 to about 1.6:1.

9. The integrated circuit of claim 5 , further comprising:
a sixth metallic structure electrically coupled with the second source region; and
a seventh metallic structure over and electrically coupled with the sixth metallic structure,
wherein the seventh metallic structure and the second diffusion area overlap by a third distance in the routing direction, the third metallic structure and the second diffusion area overlap by a fourth distance in the routing direction, and the third distance is larger than the fourth distance.

10. The integrated circuit of claim 9 , wherein the second diffusion area has a second width, a ratio of the third distance to the second width ranges from about 0.75:1 to about 1:1 and a ratio of the fourth distance to the second width ranges from about 0.1:1 to about 0.33:1.

11. The integrated circuit of claim 9 , wherein a ratio of a width of the sixth metallic structure to a width of the seventh metallic structure ranges from about 1:1 to about 2:1.

12. The integrated circuit of claim 11 , wherein a ratio of the width of the sixth metallic structure to the width of the seventh metallic structure ranges from about 1.3:1 to about 1.6:1.

13. An integrated circuit comprising:
a first diffusion area for a first type transistor, the first type transistor including a first drain region and a first source region in the first diffusion area;
a second diffusion area for a second type transistor, the second diffusion area being separated from the first diffusion area, the second type transistor including a second drain region and a second source region in the second diffusion area;
a gate electrode continuously extending across the first diffusion area and the second diffusion area in a routing direction;
a first metallic structure comprising at least one first metal, the first metallic structure overlaps the first diffusion area in the routing direction and is electrically coupled with the first drain region;
a second metallic structure comprising the at least one first metal, the second metallic structure overlaps the second diffusion area in the routing direction and is electrically coupled with the second drain region;
a third metallic structure comprising at least one second metal different from the first metal, the third metallic structure having side surfaces;
a fourth metallic structure electrically coupled with the first source region; and
a fifth metallic structure over and electrically coupled with the fourth metallic structure,
wherein
the third metallic structure is over the first metallic structure, a portion of the third metallic structure that is over the first metallic structure has a substantially planar bottom surface in direct physical contact a substantially planar top surface of with the first metallic structure,
the third metallic structure is over the second metallic structure, a portion of the third metallic structure that is over the second metallic structure has a substantially planar bottom surface in direct physical contact a substantially planar top surface of with the second metallic structure,
the side surfaces of the third metallic structure are between the first metallic structure and the second metallic structure,
the side surfaces of the third metallic structure are in direct physical contact with the first metallic structure and the second metallic structure,
the fifth metallic structure and the first diffusion area overlap by a first distance in the routing direction,
the third metallic structure and the first diffusion area overlap by a second distance in the routing direction, and
the first distance is larger than the second distance.

14. The integrated circuit of claim 13 , wherein t

Assignees

• Keshavarzi Ali
• Guo Ta-Pen
• Chang Helen Shu-Hui
• Tseng Hsiang-Jen
• Lin Shyue-Shyh
• Lu Lee-Chung
• Wu Chung-Cheng
• Tien Li-Chun
• Yang Jung-Chan
• Chen Shu-Min
• Cao Min
• Hou Yung-Chin
• Taiwan Semiconductor Mfg

Inventors

• Keshavarzi Ali
• Guo Ta-Pen
• Chang Helen Shu-Hui
• Tseng Hsiang-Jen
• Lin Shyue-Shyh
• Lu Lee-Chung
• Wu Chung-Cheng
• Tien Li-Chun
• Yang Jung-Chan
• Chen Shu-Min
• Cao Min
• Hou Yung-Chin

Classifications

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10D84/85 Primary

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D89/10

  Integrated device layouts · CPC title

• H10D84/0186

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title