Conductive pillar structure for semiconductor substrate and method of manufacture

Patent metadata

Field	Value
Publication number	US-9312230-B2
Application number	US-70186810-A
Country	US
Kind code	B2
Filing date	Feb 8, 2010
Priority date	Feb 8, 2010
Publication date	Apr 12, 2016
Grant date	Apr 12, 2016

Abstract

A conductive pillar structure for a die includes a passivation layer having a metal contact opening over a substrate. A bond pad has a first portion inside the metal contact opening and a second portion overlying the passivation layer. The second portion of the bond pad has a first width. A buffer layer over the bond pad has a pillar contact opening with a second width to expose a portion of the bond pad. A conductive pillar has a first portion inside the pillar contact opening and a second portion over the buffer layer. The second portion of the conductive pillar has a third width. A ratio of the second width to the first width is between about 0.35 and about 0.65. A ratio of the second width to the third width is between about 0.35 and about 0.65.

First claim

What is claimed is:

1. A semiconductor die comprising:
a substrate;
a passivation layer having a metal contact opening over the substrate;
a bond pad having a first portion inside the metal contact opening and a second portion overlying the passivation layer, the second portion of the bond pad having a first width;
a buffer layer disposed over the bond pad, the buffer layer having a pillar contact opening with a second width to expose a portion of the bond pad; and
a conductive pillar having a first portion inside the pillar contact opening and a second portion disposed over the buffer layer, the second portion of the conductive pillar having a third width, wherein a ratio of the second width to the first width is between about 0.35 and about 0.65, and a second ratio of the second width to the third width is between about 0.35 and about 0.65.

2. The semiconductor die of claim 1 , further comprising an interconnect layer formed over the semiconductor substrate and under the passivation layer.

3. The semiconductor die of claim 2 , wherein the conductive pillar is electrically connected to the interconnect layer through the bond pad.

4. The semiconductor die of claim 1 , wherein the passivation layer includes at least one selected from the group consisting of oxide, undoped silicate glass (USG), silicon nitride and silicon oxynitride.

5. The semiconductor die of claim 1 , wherein the buffer layer comprises polyimide.

6. The semiconductor die of claim 1 , wherein the conductive pillar comprises copper or copper alloy.

7. A semiconductor die comprising:
a substrate;
a first passivation layer having a metal contact opening over the substrate;
a bond pad having a first portion and a second portion, the first portion inside the metal contact opening, the second portion overlying the first passivation layer and having a first width;
a second passivation layer overlying the first passivation layer, partially covering second portion of the bond pad and leaving a surface of the bond pad exposed;
a buffer layer overlying the second passivaton layer and a part of the second portion of the bond pad, the buffer layer having a pillar contact opening with a second width over a part of the exposed surface of the bond pad; and
a conductive pillar having a first portion and a second portion, the first portion inside the pillar contact opening of the buffer layer, the second portion above the first portion having a third width,
wherein a ratio of the second width to the first width is between about 0.35 and about 0.65 and a second ratio of the second width to the third width is between about 0.35 and about 0.65.

8. The semiconductor die of claim 7 , wherein the second passivation layer has an opening with a fourth width to expose the second bond pad, the fourth width is substantially wider than the third width.

9. The semiconductor die of claim 7 , wherein the third width is from about 55 μm to about 130 μm.

10. The semiconductor die of claim 7 , wherein the passivation layer includes at least one selected from the group consisting of oxide, undoped silicate glass (USG), silicon nitride and silicon oxynitride.

11. The semiconductor die of claim 7 , wherein the buffer layer comprises polyimide.

12. The semiconductor die of claim 7 , further comprising multiple said conductive pillars each being in a respective pillar contact opening over a respective bond pad, a pitch defined between adjacent conductive pillars being from about 125 μm to about 250 μm.

13. A method of forming a conductive pillar structure, said method comprising:
forming a passivation layer over the substrate, the passivation layer having a metal contact opening;
forming a bond pad over the passivation layer, the bond pad having a first portion inside the metal contact opening and a second portion with a first width above of the first portion;
forming a buffer layer overlying the bond pad, the buffer layer having a pillar contact opening with a second width to partially expose the second portion of the bond pad; and
forming a conductive pillar in the pillar contact opening and overlying a portion of the buffer layer, wherein the conductive pillar overlying the buffer layer has a third width,
wherein a ratio of the second width to the first width is between about 0.35 to about 0.65,
and a second ratio of the second width to the third width is between about 0.35 and about 0. 65.

14. The method of claim 13 , further comprising:
forming a second passivation layer overlying the first passivation layer, partially covering the second portion of the bond pad and leaving a surface of the second portion of the bond pad exposed.

15. The method of claim 14 , wherein the second passivation layer has an opening with a fourth width to expose the second portion of the bond pad, the fourth width is narrower than the third width.

16. The method of claim 13 , wherein the passivation layer includes at least one selected from the group consisting of oxide, undoped silicon glass (USG), silicon nitride and silicon oxynitride.

17. The method of claim 13 , wherein the buffer layer comprises polyimide.

18. The method of claim 13 , wherein the conductive pillar comprises copper or copper alloy.

19. The method of claim 13 , further comprising forming multiple said conductive pillars each being in a respective pillar contact opening over a respective bond pad at a pitch defined between adjacent conductive pillars being from about 125 μm to about 250 μm.

20. The method of claim 13 , wherein the conductive pillar is formed to be electrically contacted to an interconnect layer through the bond pad.

21. The semiconductor die of claim 4 , wherein the passivation layer includes undoped silicate glass (USG).

22. The semiconductor die of claim 4 , wherein the passivation layer includes silicon oxynitride.

Assignees

• Chen Chih-Hua
• Chen Chen-Shien
• Kuo Chen-Cheng
• Taiwan Semiconductor Mfg

Inventors

• Chen Chih-Hua
• Chen Chen-Shien
• Kuo Chen-Cheng

Classifications

• H10W80/314

  characterized by direct bonding of pads or other interconnections · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/07236

  Soldering or alloying · CPC title

• H10W72/01953

  by etching · CPC title

• H10W72/01938

  in gaseous form, e.g. by CVD or PVD · CPC title