Methods of forming a TSV wafer with improved fracture strength

US9312205B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9312205-B2
Application numberUS-201414195940-A
CountryUS
Kind codeB2
Filing dateMar 4, 2014
Priority dateMar 4, 2014
Publication dateApr 12, 2016
Grant dateApr 12, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method including forming a through-substrate via through a thickness of a substrate, the thickness of the substrate is measured from a front side of the substrate to a back side of the substrate, removing a first portion of the substrate to form an opening in the back side of the substrate such that a second portion of the substrate remains in direct contact surrounding a vertical sidewall of the through-substrate via, and filling the opening with an alternate material having a lower modulus of elasticity than the substrate.

First claim

Opening claim text (preview).

What is claimed is: 1. A method comprising: forming through-substrate vias through a thickness of a substrate and forming semiconductor devices on a front side of the substrate, the thickness of the substrate being measured from the front side of the substrate to a back side of the substrate; removing a first portion of the substrate to form an opening that extends a predetermined depth into the back side of the substrate and that defines a second portion of the substrate, the second portion remaining in direct contact with and laterally surrounding a vertical sidewall of one of the through-substrate vias; filling the opening with an alternate material having a lower modulus of elasticity than the substrate such that the alternate material extends laterally between adjacent second portions that laterally surround adjacent through-substrate vias, the alternate material being at least as thermally conductive as the substrate; and polishing the back side of the substrate so that an exposed surface of the alternate material is essentially co-planar with the back side of the substrate. 2. The method of claim 1 , the filling of the opening with the alternate material being carried out at a process temperature less than or equal to 400° C. 3. The method of claim 1 , the alternate material comprising silicon or germanium and being polycrystalline or amorphous. 4. The method of claim 1 , the second portion extending laterally from the vertical sidewall of the one of the through-substrate vias to the alternate material by a distance greater than or equal to a diameter or a width of the through-substrate via. 5. The method of claim 1 , the removing of the first portion of the substrate to form the opening in the back side of the substrate being performed such that the opening has a depth that is less than or equal to approximately 50% of the thickness of the substrate. 6. The method of claim 1 , further comprising: forming metal contacts on the back side of the substrate in direct contact with the through-substrate vias. 7. A method comprising: forming an array of through-substrate vias through a thickness of a single crystal silicon substrate and forming semiconductor devices on a front side of the single crystal silicon substrate, the through-substrate vias extending vertically from the front side of the substrate to a back side of the substrate; removing a first portion of the substrate to form an opening that extends a predetermined depth into the back side of the substrate and that defines a second portion of the substrate, the second portion containing the array and remaining in direct contact with and laterally surrounding vertical sidewalls of the through-substrate vias; filling the opening with an alternate material to improve a durability of the single crystal silicon substrate and reduce a potential for cracking during fabrication, the alternate material having a lower modulus of elasticity than the single crystal silicon substrate; and polishing the back side of the substrate so that an exposed surface of the alternate material is essentially co-planar with the back side of the substrate. 8. The method of claim 7 , the filling of the opening with the alternate material being carried out at a process temperature less than or equal to 400° C. 9. The method of claim 7 , the alternate material comprising silicon or germanium and being polycrystalline or amorphous. 10. The method of claim 7 , the alternate material being at least as thermally conductive as the single crystal silicon substrate. 11. The method of claim 7 , the alternate material being physically separated from any of the through-substrate vias by a distance greater than or equal to a diameter or a width of the through-substrate vias. 12. The method of claim 7 , further comprising: forming metal contacts on the back side of the substrate in direct contact with the through-substrate vias. 13. A method comprising: forming through-substrate vias through a thickness of a substrate and forming semiconductor devices on a front side of the substrate, the thickness of the substrate being measured from the front side of the substrate to a back side of the substrate; removing a first portion of the substrate to form an opening that extends a predetermined depth into the back side of the substrate and that defines a second portion of the substrate, the second portion remaining in direct contact with and laterally surrounding a vertical sidewall of one of the through-substrate vias such that the vertical sidewall is physically separated from the opening by a distance that is at least equal to a width of the through-substrate via, and the predetermined depth being approximately one-half the thickness of the substrate; filling the opening with an alternate material having a lower modulus of elasticity than the substrate such that the alternate material extends laterally between adjacent second portions that laterally surround adjacent through-substrate vias, the alternate material being at least as thermally conductive as the substrate; and polishing the back side of the substrate so that an exposed surface of the alternate material is essentially co-planar with the back side of the substrate. 14. The method of claim 13 , the filling of the opening with the alternate material being carried out at a process temperature less than or equal to 400° C. 15. The method of claim 13 , the alternate material comprising silicon and being polycrystalline or amorphous. 16. The method of claim 13 , the alternate material comprising aerogel. 17. The method of claim 13 , the alternate material comprising a metal. 18. The method of claim 13 , further comprising: forming metal contacts on the back side of the substrate in direct contact with the through-substrate vias and physically separated from the alternate material.

Assignees

Inventors

Classifications

  • comprising use of blind vias during the manufacture · CPC title

  • Top-view shapes · CPC title

  • comprising ring-shaped isolation structures outside of the via holes · CPC title

  • protecting against mechanical damage (H10W76/00, H10W74/00 take precedence) · CPC title

  • Barrier, adhesion or liner layers · CPC title

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What does patent US9312205B2 cover?
A method including forming a through-substrate via through a thickness of a substrate, the thickness of the substrate is measured from a front side of the substrate to a back side of the substrate, removing a first portion of the substrate to form an opening in the back side of the substrate such that a second portion of the substrate remains in direct contact surrounding a vertical sidewall of…
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification H10W20/20. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 12 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).