Replacement metal gate stack for diffusion prevention

Patent metadata

Field	Value
Publication number	US-9312136-B2
Application number	US-201414199045-A
Country	US
Kind code	B2
Filing date	Mar 6, 2014
Priority date	Mar 6, 2014
Publication date	Apr 12, 2016
Grant date	Apr 12, 2016

Abstract

A method of forming a semiconductor structure includes depositing a gate dielectric layer lining a recess of a gate structure formed on a substrate with a first portion of the gate dielectric layer covering sidewalls of the recess and a second portion of the gate dielectric layer covering a bottom of the recess. A protective layer is deposited above the gate dielectric layer and then recessed selectively to the gate dielectric layer so that a top surface of the protective layer is below of the recess. The first portion of the gate dielectric layer is recessed until a top of the first portion of the gate dielectric layer is approximately coplanar with the top surface of the protective layer. The protective layer is removed and a conductive barrier is deposited above the recessed first portion of the gate dielectric layer to cut a diffusion path to the gate dielectric layer.

First claim

The invention claimed is:

1. A method of forming a semiconductor structure, the method comprising:
depositing a gate dielectric layer lining a recess of a gate structure formed on a substrate, a first portion of the gate dielectric layer covering sidewalls of the recess and a second portion of the gate dielectric layer covering a bottom of the recess;
depositing a protective layer above the gate dielectric layer, the protective layer substantially filling the recess;
recessing the protective layer selectively to the gate dielectric layer, wherein a top surface of the protective layer is below of the recess;
recessing the first portion of the gate dielectric layer until a top of the first portion of the gate dielectric layer is approximately coplanar with the top surface of the protective layer, wherein the protective layer protects the second portion of the gate dielectric layer while recessing the first portion of the gate dielectric layer;
removing the protective layer;
depositing a conductive barrier above the recessed first portion of the gate dielectric layer;
depositing a metal gate above the conductive barrier; and
forming a capping layer above the metal gate, wherein the conductive barrier separates the capping layer from the recessed first portion of the gate dielectric layer.

2. The method of claim 1 , further comprising:
depositing a sacrificial layer above the gate dielectric layer prior to depositing the protective layer;
recessing the sacrificial layer while recessing the first portion of the gate dielectric layer until a top portion of the sacrificial layer is approximately coplanar with the top surface of the protective layer;
protecting the gate dielectric layer with the sacrificial layer while removing the protective layer; and
removing the sacrificial layer prior to depositing the conductive barrier.

3. The method of claim 1 , wherein a length of the gate structure is equal or less than 20 nm.

4. The method of claim 1 , wherein depositing the protective layer comprises depositing an organic spin material.

5. The method of claim 1 , wherein recessing the protective layer comprises forming an etch stop indicator for the recessing of the first portion of the gate dielectric layer.

6. The method of claim 5 , wherein recessing the protective layer comprises recessing the protective layer until the protective layer has a thickness ranging from approximately 1 nm to approximately 100 nm.

7. The method of claim 1 , wherein depositing the conductive barrier comprises depositing an n-type workfunction metal on the recessed gate dielectric layer.

8. The method of claim 1 , wherein depositing a conductive barrier above the recessed first portion of the gate dielectric layer comprises depositing a conductive barrier above the recessed first portion of the gate dielectric layer to prevent diffusion of oxygen atoms and hydroxide ions from the capping layer to the gate dielectric layer.

Assignees

• IBM

Inventors

• Ando Takashi
• Faltermeier Johnathan E
• Fan Su Chen
• Kanakasabapathy Sivananda K
• Ok Injo
• Yamashita Tenko

Classifications

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10D86/011

  comprising FinFETs · CPC title

• H10D84/0158

  the components including FinFETs · CPC title

• H10D84/0142

  the gate conductors having different shapes or dimensions · CPC title

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title