Circuit arrangement and method for testing same

Patent metadata

Field	Value
Publication number	US-9311203-B2
Application number	US-201213567141-A
Country	US
Kind code	B2
Filing date	Aug 6, 2012
Priority date	Aug 11, 2011
Publication date	Apr 12, 2016
Grant date	Apr 12, 2016

Abstract

The invention relates to a circuit arrangement and to a method for testing same. A circuit arrangement is provided that includes a plurality of functional units which are coupled by at least one streaming data bus. Each of the functional units includes a plurality of hardware modules and a switch matrix. At least one of the streaming data busses is provided with a data width of at least that of the widest hardware module of any of the functional units of the circuit arrangement. The switch matrices are configurable to establish a streaming data path between and through the plurality of functional units which is used as a test link for any of the hardware modules of the circuit arrangement. The invention provides for non-intrusive real-time tracing in SoCs with a minimum of additional hardware resources and at low cost in terms of die size and power consumption.

First claim

What is claimed is:

1. A circuit arrangement comprising:
a plurality of functional units that are coupled together by at least one streaming data bus, wherein each of the functional units comprise a plurality of hardware modules and a switch matrix, wherein the switch matrix has at least one streaming data input and at least one streaming data output and is connected between a streaming data input and a streaming data output of the respective functional unit and is further coupled to each of the hardware modules of the respective functional unit so that by configuring the switch matrix a streaming data path is established between and through the plurality of functional units;
wherein at least one of the at least one streaming data bus has a data width of at least that of the widest hardware module of any of the functional units of the circuit arrangement to be configurable as a test link for any of the hardware modules.

2. The circuit arrangement of claim 1 , wherein the plurality of functional units are coupled together by a single streaming data bus, and wherein the switch matrices are configurable to connect a single one of the hardware modules that is to be tested between the single streaming data input and the single streaming data output while detouring all of the other hardware modules of all functional units of the circuit arrangement.

3. The circuit arrangement of claim 1 , wherein the plurality of functional units are coupled together by a first streaming data bus and a second streaming data bus, and wherein at least one of the first and second streaming data busses has a data width of at least that of the widest hardware module of any of the functional units of the circuit arrangement, for use as a test link.

4. The circuit arrangement of claim 3 , wherein the switch matrices are configurable to connect a single one of the hardware modules to be tested between a second streaming data input and a second streaming data output associated with the second streaming data bus while detouring all of the other hardware modules of all functional units of the circuit arrangement.

5. The circuit arrangement of claim 3 , wherein the switch matrices are configurable to establish a first streaming data path that streams processing data through the circuit arrangement and to establish a broadcast connection at an output of a hardware module, so that downstream of the hardware module, the streaming data are supplied to both the first streaming data path for a normal processing operation, and to the second streaming data bus for detecting test data from the hardware module.

6. The circuit arrangement of claim 1 , wherein the hardware modules are selected from a group consisting of a hardware accelerator, a local memory and a local processor.

7. A method for testing integrated circuitry, comprising:
providing a circuit arrangement with a plurality of functional units that are coupled together by at least one streaming data bus, wherein each of the functional units comprise a plurality of hardware modules and a switch matrix, wherein the switch matrix has at least one streaming data input and at least one streaming data output and is connected between a streaming data input and a streaming data output of the respective functional unit and is further coupled to each of the hardware modules of the respective functional unit;
providing at least one of the streaming data busses with a data width of at least that of the widest hardware module of any of the functional units of the circuit arrangement;
configuring the switch matrices of the circuit arrangement to establish a streaming data path between and through the plurality of functional units; and
using the streaming data path as a test link for any of the hardware modules.

8. The method of claim 7 , wherein the plurality of functional units are coupled by a single streaming data bus and the method further comprises:
configuring the switch matrices of the circuit arrangement to establish a streaming data path that passes from the streaming data input through a single one of the hardware modules that is to be tested and to the streaming data output while detouring all of the other hardware modules of all functional units of the circuit arrangement;
feeding a test sequence from the input to the hardware module to be tested; and
detecting test data at the streaming data output.

9. The method of claim 7 , wherein the plurality of functional units are coupled by a first streaming data bus and a second streaming data bus and the method further comprises:
providing the second streaming data bus with a data width of at least that of the widest hardware module of any of the functional units of the circuit arrangement, for use as a test link.

10. The method of claim 9 , further comprising:
configuring the switch matrices to connect a single one of the hardware modules to be tested between a second streaming data input and a second streaming data output while detouring all of the other hardware modules of all functional units of the circuit arrangement;
feeding a test sequence from the second streaming data input to the hardware module to be tested; and
detecting test data at the second streaming data output.

11. The method of claim 9 , further comprising:
configuring the switch matrices to establish a first streaming data path and streaming processing data through the first streaming path;
configuring the switch matrices to establish a broadcast connection at an output of a hardware module to supply streaming data downstream of the hardware module to the first streaming data path for a normal processing operation, and to a second streaming data bus; and
detecting test data from the hardware module to be tested under real-time processing conditions at a trace output of the second streaming data bus.

12. The method of claim 7 , wherein the configuration of the switch matrix in each individual functional unit is controlled by a local processor of the functional unit.

13. The method of claim 7 , wherein the configuration of the switch matrices of the individual functional units is controlled by a controller of the circuit arrangement external to the functional units.

14. A circuit arrangement, comprising:
a plurality of functional units coupled together by one or more streaming data busses, wherein each of the plurality of functional units comprise:
a plurality of hardware modules that operate alone or together to provide a function of a respective one of the functional units;
a switch matrix operably associated with the plurality of hardware modules of a respective functional unit, and configured to provide a unique switching configuration to facilitate a flow of data through or around one or more of the plurality of hardware modules of the respective functional unit,

wherein each functional unit comprises a unit streaming data input and a unit data streaming output, and wherein the unit streaming data input of a first functional unit of the plurality of functional units comprises a streaming data input of the circuit arrangement, wherein the unit streaming data output of the first functional unit is coupled to a unit streaming data input of a next functional unit of the plurality of functional units via at least one of the one or more streaming data busses, wherein a unit streaming data output of a last functional unit of the plurality of functional units comprises a streaming data output of the circuit arrangement, and wherein a unit streaming data input of the last functional unit is coupled to a unit streaming data output of a previous functional unit of the plurality of functional units, and

Assignees

• Melzer Lars
• Aue Volker
• Intel Deutschland Gmbh

Inventors

• Melzer Lars
• Aue Volker

Classifications

• G06F11/267 Primary

  Reconfiguring circuits for testing, e.g. LSSD, partitioning · CPC title