System management interrupt handling for multi-core processors

Patent metadata

Field	Value
Publication number	US-9311138-B2
Application number	US-201313799327-A
Country	US
Kind code	B2
Filing date	Mar 13, 2013
Priority date	Mar 13, 2013
Publication date	Apr 12, 2016
Grant date	Apr 12, 2016

Abstract

Technologies for system management interrupt (“SMI”) handling include a number of processor cores configured to enter a system management mode (“SMM”) in response to detecting an SMI. The first processor core to enter SMM and acquire a master thread lock sets an in-progress flag and executes a master SMI handler without waiting for other processor cores to enter SMM. Other processor cores execute a subordinate SMI handler. The master SMI handler may direct the subordinate SMI handlers to handle core-specific SMIs. The multi-core processor may set an SMI service pending flag in response to detecting the SMI, which is cleared by the processor core that acquires the master thread lock. A processor core entering SMM may immediately resume normal execution upon determining the in-progress flag is not set and the service pending flag is not set, to detect and mitigate spurious SMIs. Other embodiments are described and claimed.

First claim

The invention claimed is:

1. A multi-core processor to handle a system management interrupt generated in a computing device, the multi-core processor comprising:
a system management interrupt service pending flag, wherein the multi-core processor is to set the system management interrupt service pending flag in response to detection of the system management interrupt;
a processor core to (i) enter a system management mode in response to the detection of the system management interrupt by the multi-core processor and (ii) execute a system management interrupt handler manager in response to entrance of the system management mode, the system management interrupt handler manager to:
determine whether an in-progress flag is set, the in-progress flag to indicate another processor core of the multi-core processor has acquired a master thread lock of the computing device;
attempt to acquire the master thread lock in response to a determination that the in-progress flag is not set;
set the in-progress flag in response to acquisition of the master thread lock;
execute a master system management interrupt handler in response to the acquisition of the master thread lock;
determine whether the system management interrupt service pending flag is set in response to the determination that the in-progress flag is not set;
resume an execution mode of the processor core in response to a determination that the system management interrupt service pending flag is not set,
attempt to acquire the master thread lock in response to a determination that the system management interrupt service pending flag is set, and
clear the system management interrupt service pending flag in response to the acquisition of the master thread lock and prior to execution of the master system management interrupt handler.

2. The multi-core processor of claim 1 , further comprising a subordinate processor core, wherein the system management interrupt handler manager is further to execute the master system management interrupt handler without a wait for the subordinate processor core to enter the system management mode.

3. The multi-core processor of claim 1 , further comprising a system management interrupt status register, wherein the system management interrupt service pending flag comprises a system management interrupt service pending bit of the system management interrupt status register.

4. The multi-core processor of claim 1 , wherein the processor core comprises a subordinate processor core, the multi-core processor further comprises a master processor core different from the subordinate processor core, and the system management interrupt handler manager is further to:
execute a subordinate system management interrupt handler in response to a determination that the in-progress flag is set; and
execute the subordinate system management interrupt handler in response to failure to acquire the master thread lock;
wherein the subordinate system management interrupt handler is to:
determine whether the subordinate processor core is a source of the system management interrupt;
receive a command from the master processor core to handle the system management interrupt in response to a determination that the subordinate processor core is the source of the system management interrupt; and
handle the system management interrupt in response to receipt of the command from the master processor core.

5. The multi-core processor of claim 4 , wherein the subordinate system management interrupt handler is further to handle a machine check exception generated by a machine check architecture of the computing device.

6. The multi-core processor of claim 1 , wherein the processor core comprises a master processor core, and the master system management interrupt handler is further to:
determine whether the system management interrupt was generated by a component of the computing device other than a processor core;
determine whether the system management interrupt was generated by the master processor core; and
handle the system management interrupt in response to a determination that the system management interrupt was generated by the component of the computing device other than a processor core or a determination that the system management interrupt was generated by the master processor core, wherein to handle the system management interrupt comprises to handle a machine check exception generated by a machine check architecture of the computing device.

7. The multi-core processor of claim 1 , further comprising a subordinate processor core different from the processor core, wherein the processor core comprises a master processor core and the master system management interrupt handler is further to:
determine whether the subordinate processor core is a source of the system management interrupt;
send a command to the subordinate processor core to handle the system management interrupt in response to a determination that the subordinate processor core is the source of the system management interrupt; and
wait for the subordinate processor core to complete the handle of the system management interrupt.

8. A method for handling a system management interrupt generated in a computing device, the method comprising:
entering, by a processor core of the computing device, a system management mode of the processor core in response to detecting the system management interrupt;
determining, by the processor core, whether an in-progress flag is set, the in-progress flag to indicate another processor core of the computing device has acquired a master thread lock of the computing device;
attempting, by the processor core, to acquire the master thread lock in response to determining the in-progress flag is not set;
setting, by the processor core, the in-progress flag in response to acquiring the master thread lock; and
executing, by the processor core, a master system management interrupt handler in response to acquiring the master thread lock;
determining, by the processor core, whether a system management interrupt service pending flag of the computing device is set in response to determining the in-progress flag is not set, wherein the system management interrupt service pending flag is to be set by a processor of the computing device in response to detecting the system management interrupt;
resuming, by the processor core, an execution mode of the processor core in response to determining the system management interrupt service pending flag is not set; and
clearing, by the processor core, the system management interrupt service pending flag in response to acquiring the master thread lock and prior to executing the master system management interrupt handler;
wherein attempting to acquire the master thread lock further comprises attempting to acquire the master thread lock in response to determining the system management interrupt service pending flag is set.

9. The method of claim 8 , wherein the processor core comprises a subordinate processor core, the method further comprising:
executing, by the subordinate processor core, a subordinate system management interrupt handler in response to determining the in-progress flag is set; and
executing, by the subordinate processor core, the subordinate system management interrupt handler in response to not acquiring the master thread lock;
wherein executing the subordinate system management interrupt handler comprises:
determining, by the subordinate processor core, whether the subordinate processor core is a source of the system management interrupt;
receiving, by the subordinate processor core, a command from a master processor core of the computing device, different from the subordinate processor core, to handle the system m

Assignees

• Jayakumar Sarathy
• Kumar Mohan J
• Kinney Michael D
• Intel Corp

Inventors

• Jayakumar Sarathy
• Kumar Mohan J
• Kinney Michael D

Classifications

• G06F9/4812 Primary

  by interrupt, e.g. masked · CPC title

• G06F11/0772

  Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers · CPC title