Fabricating process of embedded circuit structure

Patent metadata

Field	Value
Publication number	US-9307651-B2
Application number	US-201213421330-A
Country	US
Kind code	B2
Filing date	Mar 15, 2012
Priority date	Jul 6, 2007
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

A fabricating process for an embedded circuit structure is provided. A through hole is formed in a core panel and penetrates the core panel. Two indent patterns are respectively formed on two opposite surfaces of the core panel. A conductive material is electroplated into the through hole and the indent patterns, so as to form a conductive channel in the through hole and two circuit patterns in the indent patterns respectively. Portions of the circuit patterns, which exceed the indent patterns respectively, are removed for planarizing the circuit patterns to be level with the two surfaces of the core panel respectively.

First claim

What is claimed is:

1. A fabricating process for an embedded circuit structure, comprising:
providing a core panel;
forming at least one through hole in the core panel, the through hole penetrating the entire thickness of the core panel;
forming a first indent pattern on a first major surface of the core panel;
forming a second indent pattern on a second major surface of the core panel, the second major surface being opposite to the first major surface of the core panel;
electroplating a conductive material into the through hole, the first indent pattern and the second indent pattern, so as to form a conductive channel in the through hole, a first circuit pattern in the first indent pattern, and a second circuit pattern in the second indent pattern, wherein portions of the first circuit pattern exceed the first major surface, portions of the second circuit pattern exceed the second major surface, and the electroplating process includes performing a chemical electroplating process at first and then performing an electrolysis electroplating process; and
removing the portions of the first circuit pattern, which exceed the first major surface, for planarizing the first circuit pattern to be level with the first major surface of the core panel, and removing the portions of the second circuit pattern, which exceed the second major surface, for planarizing the second circuit pattern to be level with the second major surface of the core panel.

2. The fabricating process for the embedded circuit structure according to claim 1 , wherein the step of forming the through hole includes a laser processing or a mechanical processing.

3. The fabricating process for the embedded circuit structure according to claim 1 , wherein the step of forming the first indent pattern and the second indent pattern includes a laser processing.

4. The fabricating process for the embedded circuit structure according to claim 1 , wherein the step of removing the portions of the first circuit pattern and the portions of the second circuit pattern includes etching or polishing.

5. The fabricating process for the embedded circuit structure according to claim 1 , wherein the conductive channel has a tubular space.

6. The fabricating process for the embedded circuit structure according to claim 5 , further comprising:
filling the tubular space of the conductive channel with a stuffing material to form a stuffing pillar.

7. The fabricating process for the embedded circuit structure according to claim 6 , further comprising:
removing portions of the stuffing pillar, which protrude from the first surface and the second surface, for planarizing two ends of the stuffing pillar to be level with the first surface and the second surface of the core panel respectively.

Assignees

• Chen Tsung-Yuan
• Chiang Shu-Sheng
• Unimicron Technology Corp

Inventors

• Chen Tsung-Yuan
• Chiang Shu-Sheng

Classifications

• H10W70/6565

  recessed into the surface of the package substrates, interposers, or redistribution layers · CPC title

• H05K3/045

  by making a conductive layer having a relief pattern, followed by abrading of the raised portions · CPC title

• Y10T29/49155

  Manufacturing circuit on or in base · CPC title

• H05K3/107 Primary

  by filling grooves in the support with conductive material (H05K3/045, H05K3/101, H05K3/1258 and H05K3/465 take precedence) · CPC title

• H05K2201/09036

  Recesses or grooves in insulating substrate · CPC title