Printed board, printed board unit, and method of manufacturing printed board

Patent metadata

Field	Value
Publication number	US-9307642-B2
Application number	US-201314108535-A
Country	US
Kind code	B2
Filing date	Dec 17, 2013
Priority date	Mar 18, 2013
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

A printed-board includes a first conductor-layer, a second conductor-layer provided to a layer different from the first conductor-layer, an insulation-layer provided between the first conductor-layer and the second conductor-layer, a plurality of through-holes that pass through the first conductor-layer, the second conductor-layer, and the insulation-layer, and a plurality of vias that are formed in the plurality of through-holes, respectively, and couple the first conductor-layer and the second conductor-layer, each of the plurality of vias including a conductor portion that occupies part of an internal space of the through-hole, and a non-conductor portion that occupies remaining part of the internal space, wherein in a given pair of vias adjacent to each other, the conductor portion of one of the pair of vias is arranged so as to face the non-conductor portion of another one of the pair of vias.

First claim

What is claimed is:

1. A printed board comprising:
a first conductor layer; a second conductor layer provided to a layer different from the first conductor layer;
an insulation layer provided between the first conductor layer and the second conductor layer;
a plurality of through holes that pass through the first conductor layer, the second conductor layer, and the insulation layer; and
a plurality of vias that are formed in the plurality of through holes, respectively, and couple the first conductor layer and the second conductor layer, each of the plurality of vias including a conductor portion that occupies part of an internal space of the through hole, and a non-conductor portion that occupies remaining part of the internal space,
wherein the conductor portion has a spiral shape;
wherein the spiral shape of the conductor portion is formed by twisting a core material with a core width corresponding to a diameter of one of the plurality of vias and a core thickness smaller than the core width.

2. The printed board according to claim 1 , wherein, in a given pair of vias adjacent to each other, the conductor portion of one of the pair of vias is arranged so as to face the non-conductor portion of another one of the pair of vias.

3. The printed board according to claim 1 , wherein the conductor portion is turned to wind in an identical direction in each of the plurality of vias.

4. The printed board according to claim 1 , wherein the non-conductor portion of each of the plurality of the vias is an insulator.

5. The printed board according to claim 1 , wherein the first conductor layer and the second conductor layer include a signal line.

6. The printed board according to claim 1 , wherein the non-conductor portion of each of the plurality of vias is a groove portion.

7. The printed board according to claim 1 , wherein the core thickness is 40% to 50% of the diameter of the one of the plurality of vias.

8. A printed board unit comprising:
a printed board and a semiconductor element mounted over a surface of the printed board:
wherein the printed board includes: a first conductor layer; a second conductor layer provided to a layer different from the first conductor layer;
an insulation layer provided between the first conductor layer and the second conductor layer;
a plurality of through holes that pass through the first conductor layer, the second conductor layer, and the insulation layer; and
a plurality of vias that are formed in the plurality of through holes, respectively, and couple the first conductor layer and the second conductor layer, each of the plurality of vias including a conductor portion that occupies part of an internal space of the through hole, and a non-conductor portion that occupies remaining part of the internal space,
wherein the conductor portion has a spiral shape;
wherein the spiral shape of the conductor portion is formed by twisting a core material with a core width corresponding to a diameter of one of the plurality of vias and a core thickness smaller than the core width.

9. The printed board unit according to claim 8 , wherein, in a given pair of vias adjacent to each other, the conductor portion of one of the pair of vias is arranged so as to face the non-conductor portion of another one of the pair of vias.

10. The printed board unit according to claim 8 , wherein the non-conductor portion of each of the plurality of vias is an insulator.

11. The printed board unit according to claim 8 , wherein the non-conductor portion of each of the plurality of vias is a groove portion.

12. The printed board unit according to claim 8 , wherein the core thickness is 40% to 50% of the diameter of the one of the plurality of vias.

13. A method of manufacturing a printed board that includes a first conductor layer, a second conductor layer provided to a layer different from the first conductor layer, and an insulation layer provided between the first conductor layer and the second conductor layer, the method comprising:
forming a plurality of through holes at a plurality of positions, the plurality of through holes passing through the first conductor layer, the second conductor layer, and the insulation layer; and
forming a plurality of vias, each having a spiral shape, in the plurality of through holes, respectively, the plurality of vias coupling the first conductor layer and the second conductor layer, each of the plurality of vias is formed in an internal space of the through hole so that a conductor portion that occupies part of the internal space and a non-conductor portion that occupies remaining part of the internal space are formed,
wherein the plurality of vias are formed by twisting a core material with a core width corresponding to a diameter of one of the plurality of vias and a core thickness smaller than the core width.

14. The method according to claim 13 , wherein, in a given pair of vias adjacent to each other, the conductor portion of one of the pair of vias is arranged so as to face the non-conductor portion of another one of the pair of vias.

15. The method according to claim 13 , wherein the core thickness is 40% to 50% of the diameter of the one of the plurality of vias.

16. The method according to claim 13 , wherein the non-conductor portion of each of the plurality of the vias is an insulator.

17. The method according to claim 13 , wherein the non-conductor portion of each of the plurality of vias is a groove portion.

Assignees

• Fujitsu Ltd

Inventors

• Tokuda Kazuhiko

Classifications

• Y10T29/49165

  by forming conductive walled aperture in base · CPC title

• H05K1/0216

  Reduction of cross-talk, noise or electromagnetic interference (grounding H05K1/0215) · CPC title

• H05K1/113

  Via provided in pad; Pad over filled via · CPC title

• H05K3/4046

  using auxiliary conductive elements, e.g. metallic spheres, eyelets, pieces of wire · CPC title

• H05K1/115 Primary

  Via connections; Lands around holes or via connections (H05K1/112 takes precedence) · CPC title