Low-noise amplifier circuit

Patent metadata

Field	Value
Publication number	US-9306505-B2
Application number	US-201214343894-A
Country	US
Kind code	B2
Filing date	Oct 8, 2012
Priority date	Oct 13, 2011
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

A low-noise amplifier (LNA) circuit utilizes the capacitive cross coupling technique with two pairs of NMOS transistors in conjunction with two cross coupled PMOS transistors to obtain a reduced noise figure. By using the cross coupling technique on the PMOS input transistor, the LNA circuit is able to reduce the noise figure below 2 dB without the use of an inductor. This LNA circuit may be used to amplify a signal in the WLAN band or the Bluetooth band, either independently or simultaneously.

First claim

The invention claimed is:

1. A low-noise amplifier circuit comprising:
a first transistor NMOS, a second transistor NMOS, a third transistor NMOS and a fourth transistor NMOS, each transistor having a source terminal, a gate terminal and a drain terminal,
the source terminal of the second transistor being coupled to the drain terminal of the first transistor,
the source terminal of the third transistor being coupled to the drain terminal of the fourth transistor,
the gate terminal of the first transistor having a first capacitive coupling to the source terminal of the fourth transistor, and
the gate terminal of the fourth transistor having a second capacitive coupling to the source terminal of the first transistor;

a fifth transistor PMOS and a sixth transistor PMOS, each transistor having a source terminal, a gate terminal and a drain terminal,
the drain terminal of the fifth transistor being coupled to the drain terminal of the second transistor,
the drain terminal of the sixth transistor being coupled to the drain terminal of the third transistor,
the source terminal of the fifth transistor having a third capacitive coupling to the source terminal of the first transistor,
the gate terminal of the fifth transistor having a fourth capacitive coupling to the source terminal of the sixth transistor or to the source terminal of the fourth transistor,
the gate terminal of the sixth transistor having a fifth capacitive coupling to the source terminal of the fifth transistor or to the source terminal of the first transistor, and
the source terminal of the sixth transistor having a sixth capacitive coupling to the source terminal of the fourth transistor.

2. The low-noise amplifier circuit according to claim 1 , wherein the source terminals of the first transistor and of the fourth transistor are inputs of the low noise amplifier circuit, and the drain terminals of the second transistor and the third transistor are outputs of the low-noise amplifier circuit.

3. The low-noise amplifier circuit according to claim 1 ,
wherein the first capacitive coupling is configured to increase an effective transconductance of the first transistor and to decrease an effective equivalent input resistance R n of the first transistor both by a factor superior or equal to two,
wherein the second capacitive coupling is configured to increase an effective transconductance of the fourth transistor and to decrease an effective equivalent input resistance of the fourth transistor both by a factor superior or equal to two,
wherein the fourth capacitive coupling is configured to increase an effective transconductance of the fifth transistor and to decrease an input resistance of the fifth transistor both by a factor superior or equal to two, and/or
wherein the fifth capacitive coupling is configured to increase an effective transconductance of the sixth transistor and to decrease an input resistance of the sixth transistor both by a factor superior or equal to two.

4. The low-noise amplifier circuit according to claim 1 , further comprising an inductive coupling to the ground.

5. The low-noise amplifier circuit according to claim 1 , wherein gate potential of the fifth and sixth transistors is fixed by a common loop circuit via two resistances, and wherein the reference voltage of the common loop is taken between outputs of the low noise amplifier circuit.

6. The low-noise amplifier circuit according to claim 1 , wherein at least one of the source terminal of the fifth or sixth transistors has a resistive coupling to a DC-Voltage, preferably with at least a wired resistor, and wherein gate potential of the first and fourth transistors is fixed by a current mirror via two resistances.

7. The low-noise amplifier circuit according to claim 1 , wherein the gate terminal of the first and/or of the fourth transistor has a resistive coupling to a DC-Voltage, or has a coupling to a DC-Voltage through a MOS transistor.

8. The low-noise amplifier circuit according to claim 1 , further configured to amplify at least one signal in the WLAN band or at least one signal in the Bluetooth band.

9. The low-noise amplifier circuit according to claim 8 , wherein noise figure values over the WLAN band and/or Bluetooth band of the low-noise amplifier circuit are inferior to 2 dB.

10. A circuit comprising:
a low-noise amplifier circuit including
a first transistor NMOS, a second transistor NMOS, a third transistor NMOS and a fourth transistor NMOS, each transistor having a source terminal, a gate terminal and a drain terminal, the source terminal of the second transistor being coupled to the drain terminal of the first transistor, the source terminal of the third transistor being coupled to the drain terminal of the fourth transistor, the gate terminal of the first transistor having a first capacitive coupling to the source terminal of the fourth transistor, and the gate terminal of the fourth transistor having a second capacitive coupling to the source terminal of the first transistor;
a fifth transistor PMOS and a sixth transistor PMOS, each transistor having a source terminal, a gate terminal and a drain terminal, the drain terminal of the fifth transistor being coupled to the drain terminal of the second transistor, the drain terminal of the sixth transistor being coupled to the drain terminal of the third transistor, the source terminal of the fifth transistor having a third capacitive coupling to the source terminal of the first transistor, the gate terminal of the fifth transistor having a fourth capacitive coupling to the source terminal of the sixth transistor or to the source terminal of the fourth transistor, the gate terminal of the sixth transistor having a fifth capacitive coupling to the source terminal of the fifth transistor or to the source terminal of the first transistor, and the source terminal of the sixth transistor having a sixth capacitive coupling to the source terminal of the fourth transistor; and

a power amplifier,
wherein the low-noise amplifier circuit input is shared with the power amplifier across a Balun.

11. A mobile device comprising:
a low-noise amplifier circuit including
a first transistor NMOS, a second transistor NMOS, a third transistor NMOS and a fourth transistor NMOS, each transistor having a source terminal, a gate terminal and a drain terminal, the source terminal of the second transistor being coupled to the drain terminal of the first transistor, the source terminal of the third transistor being coupled to the drain terminal of the fourth transistor, the gate terminal of the first transistor having a first capacitive coupling to the source terminal of the fourth transistor, and the gate terminal of the fourth transistor having a second capacitive coupling to the source terminal of the first transistor;
a fifth transistor PMOS and a sixth transistor PMOS, each transistor having a source terminal, a gate terminal and a drain terminal, the drain terminal of the fifth transistor being coupled to the drain terminal of the second transistor, the drain terminal of the sixth transistor being coupled to the drain terminal of the third transistor, the source terminal of the fifth transistor having a third capacitive coupling to the source terminal of the first transistor, the gate terminal of the fifth transistor having a fourth capacitive coupling to the source terminal of the sixth transistor or to the source terminal of the fourth transistor, the gate terminal of the sixth transistor having a fifth capacitive coupling to the source terminal of the fifth transistor or to the source terminal of the first transistor, and the source terminal of the sixth transistor having a sixth capacitive coupli

Assignees

• St Ericsson Sa

Inventors

• Rivoirard Frederic

Classifications

• H03F1/3211

  in differential amplifiers · CPC title

• H03F2203/45311

  the common gate stage of a cascode dif amp being implemented by multiple transistors · CPC title

• H03F2203/45334

  the AAC comprising one or more dif amps as feedback circuit elements · CPC title

• H03F2203/45312

  there being only one common gate stage of a cascode dif amp · CPC title

• H03F2200/451

  the amplifier being a radio frequency amplifier · CPC title