Vibrator And Vibrator Device
US-2024039511-A1 · Feb 1, 2024 · US
US9306495B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9306495-B2 |
| Application number | US-201414170218-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 31, 2014 |
| Priority date | Jan 31, 2014 |
| Publication date | Apr 5, 2016 |
| Grant date | Apr 5, 2016 |
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A device includes a first pin configured to connect to a first terminal of a resonator, a second pin configured to connect to a second terminal of a resonator, a gain stage having a first terminal electrically connected to the first pin, and a voltage drop circuit. The voltage drop circuit includes a first transistor having an input terminal electrically connected to a second terminal of the gain stage, and a second transistor having an input terminal electrically connected to an output terminal of the first transistor, and an output terminal electrically connected to the second pin.
Opening claim text (preview).
What is claimed is: 1. A device comprising: a first pin configured to connect to a first terminal of a resonator; a second pin configured to connect to a second terminal of a resonator; a gain stage having a first terminal electrically connected to the first pin and configured to receive an voltage signal from the first pin and to output an amplified voltage signal; and a voltage drop circuit receiving the amplified voltage signal from the gain stage and outputting to the second pin configured to connect to a second terminal of a resonator a reduced voltage signal, wherein the voltage drop circuit comprises an N-type transistor in series with a P-type transistor. 2. The device of claim 1 , wherein: the N-type transistor has an input terminal electrically connected to a second terminal of the gain stage; and the P-type transistor has an input terminal electrically connected to an output terminal of the N-type transistor, and an output terminal electrically connected to the second pin. 3. The device of claim 1 , wherein: a drain electrode of the N-type transistor is electrically connected to the second terminal of the gain stage; and a drain electrode of the P-type transistor is electrically connected to the second pin. 4. The device of claim 1 , further comprising: a second gain stage having an input terminal electrically connected to an output terminal of the P-type transistor. 5. The device of claim 4 , wherein the second gain stage is a comparator. 6. The device of claim 1 , wherein the resonator is a crystal resonator. 7. A device comprising: a resonator; and an oscillator circuit comprising: a first pin electrically connected to a first terminal of the resonator; a second pin electrically connected to a second terminal of the resonator; a gain stage having a first terminal electrically connected to the first pin; and a voltage drop circuit having a first terminal electrically connected to a second terminal of the gain stage and a second terminal electrically connected to the second pin, wherein the voltage drop circuit comprises an N-type transistor in series with a P-type transistor. 8. The device of claim 7 , wherein: the N-type transistor comprises: a gate electrode electrically connected to a first voltage supply node; a drain electrode electrically connected to the second terminal of the gain stage; and a source electrode; and the P-type transistor comprises: a gate electrode electrically connected to a second voltage supply node; a drain electrode electrically connected to the second pin; and a source electrode electrically connected to the source electrode of the N-type transistor. 9. The device of claim 7 , wherein the oscillator circuit further comprises: a second gain stage electrically connected to the second terminal of the voltage drop circuit. 10. The device of claim 9 , wherein the second gain stage is a comparator. 11. The device of claim 10 , further comprising: a clocked circuit integrated with the oscillator circuit and configured to receive a clock signal based on output of the comparator. 12. The device of claim 7 , further comprising: at least one electrostatic discharge protection circuit electrically connected to the first pin or the second pin. 13. A method comprising: (a) receiving a first periodic signal in a first voltage range from a resonator; (b) amplifying the first periodic signal to generate a second periodic signal in a second voltage range by a gain stage; (c) reducing voltage range of the second periodic signal by a voltage drop circuit having an N-type transistor in series with a P-type transistor, the voltage drop circuit generating a third periodic signal in a third voltage range; and (d) returning the third periodic signal to the resonator. 14. The method of claim 13 , wherein: (a) includes receiving the first periodic signal from a crystal resonator. 15. The method of claim 13 , wherein: (b) includes amplifying the first periodic signal to generate the second periodic signal by an inverter. 16. The method of claim 13 , wherein: (c) includes reducing the voltage range of the second periodic signal by at least one threshold voltage of the P-type transistor and one threshold voltage of the N-type transistor. 17. The method of claim 13 , further comprising: (e) generating a clock signal by a second gain stage based on the third periodic signal. 18. The method of claim 17 , wherein: (e) includes generating the clock signal by a comparator. 19. The method of claim 17 , further comprising: (f) outputting the clock signal to a clocked circuit. 20. The method of claim 19 , wherein: (f) includes outputting the clock signal to a digital circuit integrated in a same integrated circuit (IC) with the gain stage and the voltage drop circuit.
Amplitude or AM detection · CPC title
active element in amplifier being semiconductor device ({H03B5/323, H03B5/326} , H03B5/38 take precedence) · CPC title
the amplifier comprising field effect transistors (H03B5/366 takes precedence) · CPC title
being a piezoelectric resonator (selection of piezoelectric material H10N30/00) · CPC title
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