Advanced forming method and structure of local mechanical strained transistor

Patent metadata

Field	Value
Publication number	US-9306065-B2
Application number	US-201414587679-A
Country	US
Kind code	B2
Filing date	Dec 31, 2014
Priority date	Jun 9, 2006
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

Embodiments of the invention provide a semiconductor fabrication method and a structure for strained transistors. A method comprises forming a stressor layer over a MOS transistor. The stressor layer is selectively etched over the gate electrode, thereby affecting strain conditions within the MOSFET channel region. An NMOS transistor may have a tensile stressor layer, and a PMOS transistor may have compressive stressor layer.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor substrate having an upper surface;
a first isolation region and a second isolation region in the substrate;
a doped source region in the semiconductor substrate and lying beneath the upper surface of the semiconductor substrate;
a doped drain region in the semiconductor substrate and lying beneath the upper surface of the semiconductor substrate;
a channel region in the semiconductor substrate betwee…

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Chen Chien-Hao
• Lee Tze-Liang

Classifications

• H10D64/01326

  Electricity · mapped topic

• H10D84/856

  Electricity · mapped topic

• H10D84/0167

  Electricity · mapped topic

• H10D84/038

  Electricity · mapped topic

• H10D62/832

  Electricity · mapped topic