Nitride spacer for protecting a fin-shaped field effect transistor (finFET) device

US9306036B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9306036-B2
Application numberUS-201313953833-A
CountryUS
Kind codeB2
Filing dateJul 30, 2013
Priority dateJul 30, 2013
Publication dateApr 5, 2016
Grant dateApr 5, 2016

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Abstract

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Approaches for protecting a semiconductor device (e.g., a fin field effect transistor device (FinFET)) using a nitride spacer are provided. Specifically, a nitride spacer is formed over an oxide and a set of fins of the FinFET device to mitigate damage during subsequent processing. The nitride spacer is deposited before the block layers to protect the oxide on top of a set of gates in an open area of the FinFET device uncovered by a photoresist. The oxide on top of each gate will be preserved throughout all of the block layers to provide hardmask protection during subsequent source/drain epitaxial layering. Furthermore, the fins that are open and uncovered by the photoresist or the set of gates remain protected by the nitride spacer. Accordingly, fin erosion caused by amorphization of the fins exposed to resist strip processes is prevented, resulting in improved device yield.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for forming a device, the method comprising: forming a set of gate structures over a set of fins, each of the set of gate structures comprising a nitride capping layer; forming an oxide over the nitride capping layer; forming a nitride spacer over the oxide, wherein fins that are uncovered by the set of gate structures are covered by the nitride spacer; and forming at least one source/drain epitaxial layer on the device.…

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What does patent US9306036B2 cover?
Approaches for protecting a semiconductor device (e.g., a fin field effect transistor device (FinFET)) using a nitride spacer are provided. Specifically, a nitride spacer is formed over an oxide and a set of fins of the FinFET device to mitigate damage during subsequent processing. The nitride spacer is deposited before the block layers to protect the oxide on top of a set of gates in an open a…
Who is the assignee on this patent?
Globalfoundries Inc
What technology area does this patent fall under?
Primary CPC classification H10P14/6548. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 05 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).