Method of forming self-aligned metal gate structure in a replacement gate process using tapered interlayer dielectric

Patent metadata

Field	Value
Publication number	US-9306032-B2
Application number	US-201314062909-A
Country	US
Kind code	B2
Filing date	Oct 25, 2013
Priority date	Oct 25, 2013
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

A method for manufacturing a semiconductor device includes following steps. A substrate having at least a transistor embedded in an insulating material formed thereon is provided. The transistor includes a metal gate. Next, an etching process is performed to remove a portion of the metal gate to form a recess and to remove a portion of the insulating material to form a tapered part. After forming the recess and the tapered part of the insulating material, a hard mask layer is formed on the substrate to fill up the recess. Subsequently, the hard mask layer is planarized.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor device, comprising:
providing a substrate having at least a transistor embedded in an insulating material formed thereon, the transistor comprising a metal gate and the insulating material comprising at least a spacer, a contact etch stop layer (CESL) and an inter-layer dielectric (ILD) layer;
performing an etching process to remove a portion of the metal gate to form a recess and to remove a portion of the spacer, a portion of the CESL and a portion of the ILD layer to form a tapered part, wherein the metal gate is exposed at a bottom of the recess and the tapered part is formed on a top of the recess;
forming a hard mask layer on the substrate to fill up the recess; and
planarizing the hard mask layer.

2. The method for manufacturing the semiconductor device according to claim 1 , wherein the etching process comprises at least a dry etching process.

3. The method for manufacturing the semiconductor device according to claim 1 , wherein the metal gate comprises at least a gap-filling metal layer, a multiple work function metal layer, and a high dielectric constant (high-k) gate dielectric layer.

4. The method for manufacturing the semiconductor device according to claim 3 , wherein the etching process further comprises:
performing a metal etching process to remove a portion of the gap-filling metal layer and the multiple work function metal layer; and
performing an insulating material etching process to remove the portion of the ILD layer, the CESL and the spacer.

5. The method for manufacturing the semiconductor device according to claim 4 , wherein the insulating material etching process comprises C x H y F z .

6. The method for manufacturing the semiconductor device according to claim 4 , wherein the metal etching process and the insulating material etching process are performed in-situ.

7. The method for manufacturing the semiconductor device according to claim 4 , wherein the metal etching process further comprises:
performing a first metal etching step to remove a portion of the gap-filling metal layer; and
performing a second metal etching step to remove a portion of the multiple work function metal layer.

8. The method for manufacturing the semiconductor device according to claim 7 , wherein the gap-filling metal layer entirely covers a surface of the ILD layer, the CESL and the spacer of the insulating material, and the multiple work function metal layer and the high-k dielectric layer are formed between the gap-filling metal layer and the insulating material.

9. The method for manufacturing the semiconductor device according to claim 8 , wherein the first metal etching step stops at a surface of the multiple work function metal layer.

10. The method for manufacturing the semiconductor device according to claim 8 , wherein the second metal etching step stops at a surface of the high-k dielectric layer.

11. The method for manufacturing the semiconductor device according to claim 7 , wherein the first metal etching step and the second metal etching step are performed in-situ.

12. The method for manufacturing the semiconductor device according to claim 7 , wherein the first metal etching step comprises Cl 2 and SF 6 .

13. The method for manufacturing the semiconductor device according to claim 7 , wherein the second metal etching step comprises Cl 2 and BCl 3 .

Assignees

• United Microelectronics Corp

Inventors

• Lin Ching-Ling
• Huang Chih-Sen
• Tsao Po-Chao
• Hung Ching-Wen
• Wu Jia-Rong
• Lin Chien-Ting

Classifications

• H10D64/01354

  passivation or protection of the electrode, e.g. using re-oxidation · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10D30/797

  being in source or drain regions, e.g. SiGe source or drain · CPC title

• H10D30/0275

  forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions · CPC title