Method of making a semiconductor device

Patent metadata

Field	Value
Publication number	US-9305844-B2
Application number	US-201514626573-A
Country	US
Kind code	B2
Filing date	Feb 19, 2015
Priority date	Feb 22, 2013
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

Some embodiments include a semiconductor device having a stack structure including a plurality of alternating tiers of dielectric material and poly-silicon formed on a substrate. Such a semiconductor device may further include at least one opening having a high aspect ratio and extending into the stack structure to a level adjacent the substrate, a first poly-silicon channel formed in a lower portion of the opening adjacent the substrate, a second poly-silicon channel formed in an upper portion of the opening, and WSiX material disposed between the first poly-silicon channel and the second poly-silicon channel in the opening. The WSiX material is adjacent to the substrate, and can be used as an etch-landing layer and a conductive contact to contact both the first poly-silicon channel and the second poly-silicon channel in the opening. Other embodiments include methods of making semiconductor devices.

First claim

What is claimed is:

1. A method of making a semiconductor device, comprising:
forming a first stack structure over a substrate, the first stack structure including a first plurality of alternating tiers of dielectric material and conductive material;
forming a first opening in the first stack structure to a level adjacent the substrate;
filling the first opening with poly-silicon to form a first poly-silicon channel;
removing an upper portion of the first poly-silicon channel to form a recess in the first opening;
forming WSiX material in the recess and in contact with the first poly-silicon channel;
forming a second stack structure over the first stack structure and the WSiX material, the second stack structure including a second plurality of alternating tiers of dielectric material and conductive material;
forming a second opening in the second stack structure that exposes a portion of the WSiX material in the recess in the first opening, wherein the WSiX material controls further etching as an etch-landing material; and
filling the second opening with poly-silicon to form a second poly-silicon channel in contact with the WSiX.

2. The method of claim 1 , wherein the WSiX material completely separates the first poly-silicon channel and the second poly-silicon channel.

3. The method of claim 1 , wherein the dielectric material comprises tetraethyl orthosilicate (TEOS).

4. The method of claim 1 , wherein the dielectric material comprises silicon oxide.

5. The method of claim 1 , wherein the WSiX material conductively contacts both the first poly-silicon channel and the second poly-silicon channel.

6. The method of claim 1 , further comprising forming a first isolation liner on an inside wall of the first opening prior to filling the first opening with poly-silicon to form the first poly-silicon channel.

7. The method of claim 1 , further comprising forming a second isolation liner on an inside wall of the second opening, prior to filling the second opening with poly-silicon to form the second poly-silicon channel.

8. The method of claim 1 , further comprising planarizing the first stack structure and the WSiX material to expose the portion of the WSiX material prior to forming the second stack structure over the first stack structure and the WSiX material.

9. The method of claim 8 , wherein the planarizing of the first stack structure and the WSiX material comprises planarizing the first stack structure and the WSiX material by using a chemical mechanical planarization (CMP).

10. The method of claim 8 , wherein a portion of the WSiX material on a top surface of the first stack structure is removed by the CMP.

11. The method of claim 1 , wherein the second opening has a high aspect ratio.

12. The method of claim 1 , wherein the second opening is formed to have a depth greater than 2 microns and a width less than 70 nanometers.

13. The method of claim 1 , wherein forming the WSiX material in the recess comprises filling the recess.

14. A method of making a semiconductor device, comprising:
forming a first stack structure including a first plurality of alternating tiers of dielectric material and poly-silicon on a substrate, the first stack structure including a first opening extending to a level adjacent the substrate, and the first opening including a first poly-silicon channel within a lower portion thereof and WSiX material within an upper portion thereof, the WSiX material contacting the first poly-silicon channel;
forming a second stack structure including a second plurality of alternate tiers of dielectric material and poly-silicon on the first stack structure and the WSiX material;
forming a second opening in the second stack structure to expose a portion of the WSiX material in the first opening of the first stack structure; and
depositing poly-silicon in the second opening to form a second poly-silicon channel in contact with the WSiX material.

15. The method of claim 14 , wherein the first opening is formed by a dry or wet etching.

16. The method of claim 14 , wherein the second opening is formed by a dry or wet etching.

17. The method of claim 14 , wherein the depositing comprises filling the second opening with the poly-silicon to form the second poly-silicon channel.

18. The method of claim 14 , further comprising forming a first isolation liner on an inside wall of the first opening by an In Situ Steam Generation (ISSG) process or a High Temperature Oxide (HTO) process.

19. The method of claim 14 , further comprising forming a second isolation liner on an inside wall of the second opening by an ISSG process or a HTO process prior to depositing poly-silicon in the second opening to form the second poly-silicon channel.

20. The method of claim 14 , wherein the WSiX material completely separates the first poly-silicon channel and the second poly-silicon channel.

Assignees

• Micron Technology Inc

Inventors

• Zhu Hongbin
• Haller Gordon
• Long Paul D

Classifications

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10D30/026

  having laterally-coplanar source and drain regions, a gate at the sides of the bulk channel, and both horizontal and vertical current flow (of LDMOS H10D30/0289) · CPC title

• H10D30/025

  of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318) · CPC title

• H10D84/0128

  Manufacturing their channels · CPC title

• H10D84/038 Primary

  using silicon technology, e.g. SiGe · CPC title