Methods of fabricating semiconductor devices including fin-shaped active regions

Patent metadata

Field	Value
Publication number	US-9305825-B2
Application number	US-201414175212-A
Country	US
Kind code	B2
Filing date	Feb 7, 2014
Priority date	Feb 8, 2013
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

A method of manufacturing a semiconductor device includes forming a plurality of fins by forming a plurality of first device isolating trenches repeated at a first pitch in a substrate, forming a plurality of fin-type active areas protruding from a top surface of a first device isolating layer by forming the first device isolating layer in the plurality of first device isolating trenches, forming a plurality of second device isolating trenches at a pitch different from the first pitch by etching a portion of the substrate and the first device isolating layer, and forming a second device isolating layer in the plurality of second device isolating trenches, so as to form a plurality of fin-type active area groups separated from each other with the second device isolating layer therebetween.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
forming a plurality of first device isolating trenches in a substrate to define a plurality of fins;
forming a plurality of fin-type active areas protruding from a top surface of a first device isolating layer by forming the first device isolating layer in the plurality of first device isolating trenches;
forming at least one second device isolating trench in the substrate by etching a portion of the substrate and a portion of the first device isolating layer;
filling the at least one second device isolating trench with an insulating layer;
implanting an impurit into the plurality of fin-type active areas; and
after implanting the impurity, forming a second device isolating layer in the at least one second device isolating trench by removing a portion of the insulating layer so as to form a plurality of fin-type active area groups that are separated from each other with the second device isolating layer therebetween.

2. The method of claim 1 , wherein the plurality of first device isolating trenches are repeated at a first pitch in the substrate, and the at least one second device isolating trench comprises a plurality of second device isolating trenches repeated at a second pitch greater than the first pitch.

3. The method of claim 1 , wherein a width of the at least one second device isolating trench is greater than a width of each of the plurality of first device isolating trenches.

4. The method of claim 1 , wherein a distance from a top surface of one of the plurality of fin-type active areas to a bottom surface of the second device isolating layer is greater than a distance from the top surface of the one of the plurality of fin-type active areas to a bottom surface of the first device isolating layer.

5. The method of claim 1 , wherein the plurality of fin-type active area groups respectively comprise at least one fin-type active area among the plurality of fin-type active areas.

6. The method of claim 1 , wherein the plurality of fin-type active area groups comprises:
a first fin-type active area group where the second device isolating layer is repeated at a first pitch; and
a second fin-type active area group where the second device isolating layer is repeated at a second pitch different from the first pitch.

7. The method of claim 1 , wherein the at least one second device isolating trench comprises at least two second device isolating trenches having different widths.

8. The method of claim 1 , wherein forming the plurality of fin-type active areas comprises:
forming a preliminary liner insulating layer on sidewalls and bottom surfaces of the plurality of first device isolating trenches;
forming a first preliminary device isolating layer filling the plurality of first device isolating trenches on the preliminary liner insulating layer;
planarizing the first preliminary device isolating layer by removing an upper portion of the first preliminary device isolating layer; and
forming a liner insulating layer and the first device isolating layer in the plurality of first device isolating trenches by removing a portion of the preliminary liner insulating layer and a portion of the first preliminary device isolating layer.

9. A method of manufacturing a semiconductor device, the method comprising:
forming a plurality of first device isolating trenches in a substrate to define a plurality of fins;
forming a plurality of first isolating layers in the plurality of first device isolating trenches;
forming a second device isolating trench by etching a portion of the substrate and a portion of the plurality of first isolating layers;
forming a second isolating layer in the second device isolating trench;
implanting an impurity into the plurality of fins; and
after implanting the impurity, removing a portion of the second isolating layer to form a device isolating layer in the second device isolating trench, the device isolating layer having a top surface lower than top surfaces of the plurality of fins.

10. The method of claim 9 , further comprising:
forming a liner insulating layer on sidewalls and bottom surfaces of the plurality of first device isolating trenches before forming the plurality of first isolating layers.

11. The method of claim 9 , wherein forming the second device isolating trench comprises removing at least one fin among the plurality of fins.

12. The method of claim 9 , wherein forming the second device isolating trench comprises exposing a part of the plurality of first isolating layers through the second device isolating trench.

13. The method of claim 9 , wherein the second isolating layer has a sidewall contacting a part of the plurality of first isolating layers in the second device isolating trench.

14. The method of claim 9 , wherein implanting the impurity comprises implanting p-type conductive ions or n-type conductive ions into the plurality of fins.

15. The method of claim 9 , wherein a width of the second device isolating trench is greater than a width of each of the plurality of first device isolating trenches.

16. The method of claim 9 , wherein a distance from a level of a top surface of one of the plurality of fins to a level of a bottom surface of the second device isolating trench is greater than a distance from the level of the top surface of the one of the plurality of fins to a level of a bottom surface of one of the plurality of first device isolating trenches.

17. A method of manufacturing a semiconductor device, the method comprising:
forming a plurality of first device isolating trenches in a substrate to define a plurality of fins;
forming a plurality of first isolating layers covering sidewalls of the plurality of fins in the plurality of first device isolating trenches;
forming at least one second device isolating trench by removing at least one fin among the plurality of fins, a portion of the plurality of first isolating layers, and a portion of the substrate, the at least one second device isolating trench defining a plurality of fin-type active area groups;
forming at least one second isolating layer in the at least one second device isolating trench;
implanting an impurity into the plurality of fins while covering a sidewall of at least one fin among the plurality of fins with the at least one second isolating layer; and
forming a device isolating layer in the at least one second device isolating trench by removing a top portion of the at least one second isolating layer, the device isolating layer having a top surface lower than top surfaces of the plurality of fins.

18. The method of claim 17 , wherein a distance from a level of the top surfaces of the plurality of fins to a level of a bottom surface of the at least one second device isolating trench is greater than a distance from the level of the top surfaces of the plurality of fins to a level of a bottom surface of one of the plurality of first device isolating trenches.

19. The method of claim 17 , wherein the plurality of first device isolating trenches are repeated at a first pitch in the substrate, and the at least one second device isolating trench comprises a plurality of second device isolating trenches repeated at a second pitch greater than the first pitch.

20. The method of claim 17 , wherein the plurality of fin-type active area groups comprises:
a plurality of first fin-type active area groups repeated at a first pitch; and
a plurality of second fin-type active area groups re

Assignees

• Samsung Electronics Co Ltd

Inventors

• Youn Young-Sang
• Song Myung-Geun
• Cha Ji-Hoon
• Baek Jae-Jik
• Yoon Bo-Un
• Han Jeong-Nam

Classifications

• H10P30/212

  Through-implantation · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10W10/041

  of isolation regions comprising polycrystalline semiconductor materials · CPC title

• H10W10/40

  Isolation regions comprising polycrystalline semiconductor materials · CPC title

• H10W10/0143 Primary

  comprising concurrently refilling multiple trenches having different shapes or dimensions · CPC title