Methods for forming a semiconductor device using masks with non-metallic portions

Patent metadata

Field	Value
Publication number	US-9305801-B2
Application number	US-201313789244-A
Country	US
Kind code	B2
Filing date	Mar 7, 2013
Priority date	May 16, 2012
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

A method of forming a semiconductor device can be provided by forming a mask pattern including non-metallic first spaced-apart portions that extend in a first direction on a lower target layer and non-metallic second spaced-apart portions that extend in a second direction on the lower target layer to cross-over the non-metallic first spaced-apart portions at locations. The lower target layer can be etched using the mask pattern.

First claim

What is claimed is:

1. A method of forming a semiconductor device, the method comprising:
forming a mask pattern including non-metallic first spaced-apart portions that extend in a first direction on a lower target layer and non-metallic second spaced-apart portions that extend in a second direction on the lower target layer to cross-over the non-metallic first spaced-apart portions at locations,
wherein forming the mask pattern comprises:
forming a first hard mask layer on the lower target layer, forming the first hard mask layer comprising forming an organic mask layer and forming an inorganic mask layer on the organic mask layer;
forming a non-metallic buffer pattern on the first hard mask layer, the non-metallic buffer pattern extending in the second direction;
forming a hard mask pattern extending in the first direction on the first hard mask layer and on the non-metallic buffer pattern;
etching the first hard mask layer using the hard mask pattern as an etching mask to remove portions of the inorganic mask layer exposed by the hard mask pattern thereby exposing the organic mask later and to leave an inorganic mask pattern beneath the non-metallic buffer pattern and beneath the hard mask pattern; and
removing the hard mask pattern from the non-metallic buffer pattern and from the inorganic mask pattern; and

etching the lower target layer using the mask pattern.

2. The method of claim 1 wherein etching the lower target layer further comprises:
removing upper portions of the non-metallic second spaced-apart portions of the mask pattern when etching the lower target layer.

3. The method of claim 1 wherein the non-metallic first and second spaced-apart portions are free of metals.

4. The method of claim 1 wherein the non-metallic first and second spaced-apart portions comprise respective non-metallic first and second spaced-apart line-shaped portions.

5. The method of claim 1 wherein forming the hard mask pattern comprises forming the hard mask pattern to include portions covering an isolation region beneath the lower target layer and extending between directly adjacent portions of the non-metallic buffer pattern.

6. The method of claim 1 wherein the first hard mask layer and the non-metallic buffer pattern have an etch selectivity relative to the hard mask pattern.

7. The method of claim 1 , wherein forming the mask pattern further comprises
etching exposed portions of the organic mask layer using the non-metallic buffer pattern and the inorganic mask pattern as an etching mask to expose underlying portions of the lower target layer and to form the non-metallic first and second spaced-apart portions of the mask pattern.

8. The method of claim 7 wherein the second spaced-apart portions of the mask pattern comprise the non-metallic buffer pattern.

9. The method of claim 7 wherein etching the lower target layer comprises anisotropically etching the lower target layer using the inorganic mask pattern, the underlying organic mask layer, and the non-metallic buffer pattern.

10. The method of claim 9 further comprising:
removing the mask pattern from the lower target layer.

11. The method of claim 10 further comprising:
forming filling material on the exposed portions of the lower target layer.

12. The method of claim 1 wherein the non-metallic first spaced-apart portions are spaced-apart by a first distance and the non-metallic second spaced-apart portions are spaced-apart by a second distance that is different than the first distance.

13. The method of claim 12 wherein the second distance varies across the lower target layer.

14. The method of claim 1 wherein the non-metallic first spaced-apart portions are spaced-apart by a first distance and the non-metallic second spaced-apart portions are spaced-apart by a second distance that is equal to the first distance.

15. The method of claim 1 wherein the semiconductor device comprises a Static Random Access Memory (SRAM).

16. The method of claim 1 further comprising:
forming gate electrodes prior to forming the mask pattern, wherein etching the lower target layer exposes active areas beneath the lower target layer associated with the gate electrodes.

17. The method of claim 1 wherein the non-metallic first spaced-apart portions and the non-metallic second spaced-apart portions comprise non-metallic first spaced-apart lines and non-metallic second spaced-apart lines, respectively, that extend in the first and second directions, perpendicular to one another.

18. The method of claim 1 , wherein the mask pattern includes first and second openings defined by the non-metallic first spaced-apart portions and the non-metallic second spaced-apart portions, and
wherein the first openings have a different width compared to that of the second openings, in the first direction.

19. A method of forming a semiconductor device, the method comprising:
etching a lower target layer, using a multi-level mask mesh pattern that is free of metals, to expose active areas of a substrate adjacent to metal gate structures associated with the active areas, wherein the multi-level mask mesh pattern comprises a first mask pattern and a second mask pattern that are sequentially stacked on the lower target layer,
wherein the first mask pattern has a mesh shape and comprises first spaced-apart portions that extend in a first direction and second spaced-apart portions that extend in a second direction that is different from the first direction,
wherein the first mask pattern comprises a first organic mask pattern and a first inorganic mask pattern that are sequentially stacked on the lower target layer, and each of the first organic mask pattern and the first inorganic mask pattern has the mesh shape, and
wherein the second mask pattern comprises line-shaped second inorganic mask patterns that are spaced-apart from each other, overlie respective ones of the second spaced-apart portions of the first mask pattern and extend in the second direction.

20. The method of claim 19 wherein the first organic pattern and the first inorganic mask pattern have a high etch selectivity relative to the metal gate structures.

21. The method of claim 19 further comprising:
removing the multi-level mask mesh pattern when etching the lower target layer.

22. The method of claim 19 wherein the first spaced-apart portions are spaced apart by a first amount, and the second spaced-apart portions are spaced apart by a second amount that is different from the first amount.

23. The method of claim 19 wherein the first spaced-part portions are spaced apart by a first amount, and the second spaced-apart portions are spaced apart by the first amount.

24. The method of claim 19 wherein the line-shaped second inorganic mask patterns cross over the first spaced-apart portions of the first mask pattern.

25. The method of claim 19 , wherein the first organic mask pattern has a planar upper surface.

26. The method of claim 25 , wherein the first inorganic mask pattern has a unitary structure.

27. The method of claim 19 , further comprising forming the multi-level mask mesh pattern on the lower target layer, wherein forming the multi-level mask mesh pattern comprises:
sequentially forming an organic mask layer, an inorganic mask layer and the line-shaped second inorganic mask patterns on the lower target layer;
forming line-shaped mask patterns on the line-sha

Assignees

• Sung Sughyun
• Kim Myeongcheol
• Jung Myung-Hoon
• Samsung Electronics Co Ltd

Inventors

• Sung Sughyun
• Kim Myeongcheol
• Jung Myung-Hoon

Classifications

• H10P76/405 Primary

  characterised by their composition, e.g. multilayer masks · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10P50/696 Primary

  Process specially adapted to improve the resolution of the mask · CPC title