Substrate correction device, substrate lamination device, substrate processing system, substrate correction method, substrate processing method, and semiconductor device manufacturing method
US-2024404859-A1 · Dec 5, 2024 · US
Thin wafer handling method
US9305769B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9305769-B2 |
| Application number | US-201414157210-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 16, 2014 |
| Priority date | Jun 30, 2009 |
| Publication date | Apr 5, 2016 |
| Grant date | Apr 5, 2016 |
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Abstract
Official abstract text for this publication.
A method includes receiving a carrier with a release layer formed thereon. A first adhesive layer is formed on a wafer. A second adhesive layer is formed over the first adhesive layer or over the release layer. The carrier and the wafer are bonded with the release layer, the first adhesive layer, and the second adhesive layer in between the carrier and the wafer.
First claim
Opening claim text (preview).
What is claimed is: 1. A method, comprising: forming a first adhesive layer on a wafer; forming a second adhesive layer over the first adhesive layer or over a release layer on a carrier; and bonding the carrier and the wafer with the release layer, the first adhesive layer, and the second adhesive layer in between the carrier and the wafer, wherein the bonding process is subsequent to forming the first adhesive layer on the wafer, and a peripheral portion of the wafer is free…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9305769B2 cover?
- A method includes receiving a carrier with a release layer formed thereon. A first adhesive layer is formed on a wafer. A second adhesive layer is formed over the first adhesive layer or over the release layer. The carrier and the wafer are bonded with the release layer, the first adhesive layer, and the second adhesive layer in between the carrier and the wafer.
- Who is the assignee on this patent?
- Taiwan Semiconductor Mfg
- What technology area does this patent fall under?
- Primary CPC classification H10P10/128. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Apr 05 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).