SRAM cell and cell layout method

Patent metadata

Field	Value
Publication number	US-9305633-B2
Application number	US-201414283120-A
Country	US
Kind code	B2
Filing date	May 20, 2014
Priority date	Apr 17, 2014
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

Embodiments include an array of SRAM cells, an SRAM cell, and methods of forming the same. An embodiment is an array of static random access memory (SRAM) cells including a plurality of overlapping rectangular regions. Each of overlapping rectangular regions including an entire first SRAM cell, a portion of a second adjacent SRAM cell in a first corner region of the rectangular region, and a portion of a third adjacent SRAM cell in a second corner region of the rectangular region, the second corner region being opposite the first corner region. Embodiments also include multi-finger cell layouts.

First claim

What is claimed is:

1. An array of static random access memory (SRAM) cells comprising:
a plurality of overlapping rectangular regions, each of the overlapping rectangular regions comprises:
an entire first SRAM cell;
a portion of a second adjacent SRAM cell in a first corner region of the rectangular region; and
a portion of a third adjacent SRAM cell in a second corner region of the rectangular region, the second corner region being opposite the first corner region.

2. The array of SRAM cells of claim 1 , wherein each of the overlapping rectangular regions further comprises:
a first continuous well region extending through the first SRAM cell and the portion of the second adjacent SRAM cell in the first corner region of the rectangular region; and
a second continuous well region extending through the first SRAM cell and the portion of the third adjacent SRAM cell in the second corner region of the rectangular region.

3. The array of SRAM cells of claim 2 , wherein the first continuous well region and the second continuous well region are each n-well regions; and
wherein each of the overlapping rectangular regions further comprises:
at least one p-well interposed between the first continuous n-well region and the second continuous n-well region.

4. The array of SRAM cells of claim 1 , wherein each of the overlapping rectangular regions further comprises:
a first pull-up transistor of the first SRAM cell in a third corner region of the rectangular region, the third corner region being adjacent the first corner region; and
a second pull-up transistor of the first SRAM cell in a fourth corner region of the rectangular region, the fourth corner region being adjacent the second corner region and opposite the third corner region.

5. The array of SRAM cells of claim 4 , wherein the fourth corner region is diagonally opposite the third corner region.

6. The array of SRAM cells of claim 4 , wherein the first pull-up transistor is a p-channel MOSFET (PMOS) transistor, and wherein the second pull-up transistor is a PMOS transistor.

7. The array of SRAM cells of claim 4 , wherein the first pull-up transistor comprises more than one gate electrode extending over an active area of the first pull-up transistor, and wherein the second pull-up transistor comprises more than one gate electrode extending over an active area of the second pull-up transistor.

8. The array of SRAM cells of claim 4 , wherein the first SRAM cell further comprises:
a first pull-down transistor;
a first read access transistor;
a first write access transistor;
a second pull-down transistor;
a second read access transistor; and
a second write access transistor, wherein active areas for each of the first pull-down transistor, the first read access transistor, the first write access transistor, the second pull-down transistor, the second read access transistor, and the second write access transistor are between the first pull-up transistor and the second pull-up transistor.

9. The array of SRAM cells of claim 8 , wherein the first pull-down transistor comprises:
a first gate electrode extending over a first active area of the first pull-down transistor and an active area of the first pull-up transistor; and
a second gate electrode over a second active area of the first pull-down transistor, the second active area of the first pull-down transistor separated from the first active area of the first pull-down transistor by an active area of the first read access transistor.

10. The array of SRAM cells of claim 8 , wherein the first read access transistor comprises two gate electrodes over an active area of the first read access transistor.

11. The array of SRAM cells of claim 1 , wherein the array of SRAM cells comprises an array of 6 transistor (6T) SRAM cells.

12. The array of SRAM cells of claim 1 , wherein the array of SRAM cells comprises an array of 8 transistor (8T) SRAM cells.

13. The array of SRAM cells of claim 1 , wherein the array of SRAM cells comprises an array of 10 transistor (10T) SRAM cells.

14. The array of SRAM cells of claim 1 , wherein the second corner region is diagonally opposite the first corner region.

15. A static random access memory (SRAM) cell comprising:
a first pull-up transistor having an active area in a first substrate;
a second pull-up transistor having an active area in the first substrate;
a first pull-down transistor having an active area in the first substrate; and
a first access transistor having an active area in the first substrate, wherein the active areas for the first pull-down transistor and the first access transistor are between the active areas of the first pull-up transistor and the second pull-up transistor.

16. The SRAM cell of claim 15 , wherein the active areas for the first pull-up transistor and the second pull-up transistor are n-wells, and wherein the active areas for the first pull-down transistor and the first access transistor are p-wells.

17. The SRAM cell of claim 15 , wherein the active areas for the first pull-down transistor and the first access transistor are a common active area.

18. The SRAM cell of claim 15 , wherein the active areas for the first pull-down transistor and the first access transistor are separate active areas.

19. The SRAM cell of claim 15 further comprising:
wherein the first pull-up transistor is coupled between a first supply node and a true data storage node; and
a first supply circuit configured to apply a first supply voltage to the first supply node when writing a logic low value to the true data storage node and apply a second supply voltage to the first supply node when writing a logic high value to the true data storage node.

20. The SRAM cell of claim 19 , wherein the first supply circuit is further configured to apply the second supply voltage to the first supply node when reading from the true data storage node.

21. The SRAM cell of claim 19 , wherein the first supply voltage is greater than the second supply voltage.

22. The SRAM cell of claim 19 , wherein the first pull-up transistor is a p-channel MOSFET and the first supply node is a source node of the p-channel MOSFET.

23. The SRAM cell of claim 15 further comprising:
a second pull-down transistor;
a second read access transistor, wherein the first access transistor is a first read access transistor;
a first write access transistor; and
a second write access transistor, wherein each of the first pull-up transistor, the second pull-up transistor, the first pull-down transistor, the second pull-down transistor, the first read access transistor, the second read access transistor, the first write access transistor, and the second write access transistor have more than one gate electrodes extending over their respective active areas.

24. A static random access memory (SRAM) cell comprising:
a first pull-up transistor;
a first pull-down transistor;
a first read access transistor;
a second pull-up transistor;
a second pull-down transistor; and
a second read access transistor, wherein active areas of each of the first pull-down transistor, the first read access transistor, the second pull-down transistor, and the second read access transistor have more than one gate electrodes extending over their respective active areas.

25. The SRAM cell of claim 24 , wherein active areas of each of the first pull-down transistor, the first read access transistor, the second pull-

Assignees

• St Microelectronics Int Nv

Inventors

• Grover Anuj
• Visweswaran Gangaikondan Subramani

Classifications

• H10D89/10

  Integrated device layouts · CPC title

• G11C5/02

  Disposition of storage elements, e.g. in the form of a matrix array · CPC title

• G11C11/415

  Address circuits · CPC title

• G11C11/4116

  with at least one cell access via separately connected emittors of said transistors or via multiple emittors, e.g. T2L, ECL · CPC title

• G11C11/416

  Read-write [R-W] circuits · CPC title