Semiconductor device, and microprocessor, processor, system, data storage system and memory system including the semiconductor device for generating current supplied to write path

Patent metadata

Field	Value
Publication number	US-9153318-B2
Application number	US-201313951233-A
Country	US
Kind code	B2
Filing date	Jul 25, 2013
Priority date	Apr 22, 2013
Publication date	Oct 6, 2015
Grant date	Oct 6, 2015

Abstract

A semiconductor device includes: a write current generator configured to generate a write current corresponding to a write reference voltage in a write mode and to have a negative feedback structure. The semiconductor device may further comprise a variable resistance device configured to have a resistance value that varies with the write current.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a write current generator configured to generate a write current corresponding to a write reference voltage in a write mode and to have a negative feedback structure;
a variable resistance device configured to have a resistance value that varies with the write current; and
a write reference voltage generator configured to generate the write reference voltage,
wherein the write reference voltage generator includes a digital-to-analog converter (DAC).

2. The semiconductor device of claim 1 , further comprising:
a current path configured to transfer the write current to the variable resistance device in response to a selection signal.

3. The semiconductor device of claim 1 , wherein the variable resistance device includes any of a metal oxide material and a phase-change material, and has a structure where a tunnel barrier layer is interposed between two magnetic layers.

4. A semiconductor device, comprising:
a write reference voltage generator configured to generate a write reference voltage in a write mode;
a comparison unit configured to compare a voltage at a supply node with the write reference voltage and to produce a comparison result;
a write current supplying unit configured to supply a predetermined write current to the supply node based on the comparison result of the comparison unit; and
a variable resistance device configured to have a resistance value that varies with the write current.

5. The semiconductor device of claim 4 , further comprising:
a global path configured to transfer the write current from the supply node to a coupling node in response to a global selection signal; and
a local path configured to transfer the write current from the coupling node to the variable resistance device in response to a local selection signal.

6. The semiconductor device of claim 5 , wherein the global path includes:
a global switching unit configured to switch in response to the global selection signal; and
a global bit line configured to transfer the write current to the local path through the global switching unit.

7. The semiconductor device of claim 5 , wherein the local path includes:
a local switching unit configured to switch in response to the local selection signal; and
a local bit line configured to transfer the write current to the variable resistance device through the local switching unit.

8. The semiconductor device of claim 4 , wherein the write reference voltage generator includes a digital-to-analog converter (DAC).

9. The semiconductor device of claim 4 , wherein the write current supplying unit includes a pull-up driver for driving the supply node with a predetermined driving voltage in response to the comparison result of the comparison unit.

10. The semiconductor device of claim 4 , wherein the variable resistance device includes any of a metal oxide material and a phase-change material, and has a structure where a tunnel barrier layer is interposed between two magnetic layers.

11. A semiconductor device, comprising:
a variable resistance device configured to have a resistance value that varies with a current flowing though both ends;
a current transfer path configured to transfer a write current for writing a data to the variable resistance device and a read current for reading the data to the variable resistance device;
a write circuit configured to generate the write current and supply the write current to the current transfer path in a write mode; and
a read circuit configured to generate the read current and supply the read current to the current transfer path in a read mode,
wherein the write circuit includes:
a write reference voltage generator configured to generate a write reference voltage; and
a write current generator configured to generate the write current corresponding to the write reference voltage, and to have a negative feedback structure.

12. The semiconductor device of claim 11 , wherein power sources connected to the write circuit and the read circuit supply different voltages to the write circuit and the read circuit, respectively.

13. The semiconductor device of claim 11 , wherein the write circuit further includes a write coupler that switches in response to a write enable signal and selectively transfers the write current to the current transfer path.

14. The semiconductor device of claim 11 , wherein the write current generator includes:
a comparison unit configured to compare a voltage at a supply node with the write reference voltage and to produce a comparison result; and
a write current supplying unit configured to supply the write current to the supply node based on the comparison result of the comparison unit.

15. The semiconductor device of claim 14 , wherein the write current supplying unit includes a pull-up driver configured to drive the supply node with a predetermined driving voltage in response to the comparison result of the comparison unit.

16. The semiconductor device of claim 11 , wherein the write reference voltage generator includes a digital-to-analog converter (DAC).

17. The semiconductor device of claim 11 , wherein the current transfer path includes:
a local switching unit configured to switch in response to a local selection signal;
a local bit line configured to transfer the write current or the read current to the variable resistance device through the local switching unit;
a global switching unit configured to switch in response to a global selection signal; and
a global bit line configured to transfer the write current or the read current to the local bit line through the global switching unit.

Assignees

• Sk Hynix Inc

Inventors

• Yim Hyuck-Sang

Classifications

• G11C11/16

  using elements in which the storage effect is based on magnetic spin effect · CPC title

• G11C13/0004

  comprising amorphous/crystalline phase transition cells · CPC title

• G11C13/0007

  comprising metal oxide memory material, e.g. perovskites · CPC title

• G11C13/0069 Primary

  Writing or programming circuits or methods · CPC title

• G11C11/1675

  Writing or programming circuits or methods · CPC title