Processors, methods, and systems to relax synchronization of accesses to shared memory

Patent metadata

Field	Value
Publication number	US-9304940-B2
Application number	US-201313844729-A
Country	US
Kind code	B2
Filing date	Mar 15, 2013
Priority date	Mar 15, 2013
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

A processor of an aspect includes a plurality of logical processors. A first logical processor of the plurality is to execute software that includes a memory access synchronization instruction that is to synchronize accesses to a memory. The processor also includes memory access synchronization relaxation logic that is to prevent the memory access synchronization instruction from synchronizing accesses to the memory when the processor is in a relaxed memory access synchronization mode.

First claim

What is claimed is:

1. A processor comprising:
a plurality of logical processors;
a first logical processor of the plurality, the first logical processor to execute software that includes a memory access synchronization instruction that is to synchronize accesses to a memory, wherein the memory access synchronization instruction is selected from a read-modify-write instruction, a compare-and-swap instruction, a test-and-set instruction, and a store-conditional instruction of a load-link/store-conditional pair of instructions; and
memory access synchronization relaxation logic to prevent the memory access synchronization instruction from synchronizing accesses to the memory when the processor is in a relaxed memory access synchronization mode, wherein the memory access synchronization relaxation logic comprises logic to convert the memory access synchronization instruction to an instruction selected from a store and a write.

2. The processor of claim 1 , wherein the processor has one or more architecturally-visible bits to indicate that the processor is in the relaxed memory access synchronization mode.

3. The processor of claim 2 , wherein the one or more architecturally-visible bits are accessible to software to allow the software to modify the one or more architecturally-visible bits to indicate that the processor is in the relaxed memory access synchronization mode.

4. The processor of claim 2 , wherein the one or more architecturally-visible bits correspond to the memory, and further comprising another set of one or more architecturally-visible bits which correspond to a second, different memory.

5. A processor comprising:
a plurality of logical processors;
a first logical processor of the plurality, the first logical processor to execute software that includes a memory access synchronization instruction that is to synchronize accesses to a memory, wherein the memory access synchronization instruction comprises a conditional memory access instruction selected from a conditional load instruction and a conditional store instruction; and
memory access synchronization relaxation logic to prevent the memory access synchronization instruction from synchronizing accesses to the memory when the processor is in a relaxed memory access synchronization mode, wherein the memory access synchronization relaxation logic comprises logic to convert the conditional memory access instruction to a corresponding un-conditional memory access instruction.

6. The processor of claim 5 , wherein the processor has one or more architecturally-visible bits to indicate that the processor is in the relaxed memory access synchronization mode.

7. The processor of claim 5 , wherein the one or more architecturally-visible bits are accessible to software to allow the software to modify the one or more architecturally-visible bits to indicate that the processor is in the relaxed memory access synchronization mode.

8. The processor of claim 5 , wherein the one or more architecturally-visible bits correspond to the memory, and further comprising another set of one or more architecturally-visible bits which correspond to a second, different memory.

9. A method in a processor comprising:
fetching a set of instructions for a first logical processor of a plurality of logical processors, the set of instructions including a memory access synchronization instruction to synchronize accesses to a memory, wherein fetching comprises fetching the memory access synchronization instruction which is a conditional memory access instruction selected from a conditional load instruction and a conditional store instruction;
converting the conditional memory access instruction to a corresponding un-conditional memory access instruction; and
accessing the memory from the first logical processor without respecting the synchronization of the memory access synchronization instruction.

10. The method of claim 9 , further comprising determining that the processor is in a relaxed memory access synchronization mode by checking one or more architecturally visible bits that indicate that the processor is in the relaxed memory access synchronization mode.

11. The method of claim 10 , further comprising software modifying the one or more architecturally visible bits to indicate that the processor is in a relaxed memory access synchronization mode.

12. The method of claim 9 , further comprising preventing the memory access synchronization instruction from synchronizing the accesses to the memory.

13. A method in a processor comprising:
fetching a set of instructions for a first logical processor of a plurality of logical processors, the set of instructions including a memory access synchronization instruction to synchronize accesses to a memory, wherein fetching comprises fetching the memory access synchronization instruction which is an instruction selected from a read-modify-write instruction, a compare-and-swap instruction, a test-and-set instruction, and a store-conditional instruction of a load-link/store-conditional pair of instructions;
converting the conditional memory access instruction to an instruction selected from a store and a write; and
accessing the memory from the first logical processor without respecting the synchronization of the memory access synchronization instruction.

14. A system to process instructions comprising:
an interconnect;
a processor coupled with the interconnect; and
a dynamic random access memory (DRAM) coupled with the interconnect, the DRAM to store instructions that, when executed by a machine, will cause the machine to perform operations comprising:
determining to allow a first logical processor, of a plurality of logical processors of the processor, to operate in a relaxed memory access synchronization mode when no other logical processors access the memory that the first logical processor is to prevent the memory access synchronization instruction from synchronizing accesses to; and
modifying one or more architecturally-visible bits of the processor to indicate that the first logical processor is allowed to operate in the relaxed memory access synchronization mode,
wherein, when allowed to operate in the relaxed memory access synchronization mode, the first logical processor is to prevent a memory access synchronization instruction from synchronizing accesses to a memory.

15. The system of claim 14 , wherein the instructions comprises instructions of an operating system.

16. An article of manufacture comprising a non-transitory machine-readable storage medium, the non-transitory machine-readable storage medium storing instructions that, if executed by a machine, will cause the machine to perform operations comprising:
determining to allow a first logical processor, of a plurality of logical processors of the machine, to operate in a relaxed memory access synchronization mode when no other logical processors access the memory that the first logical processor is to prevent the memory access synchronization instruction from synchronizing accesses to and
modifying one or more architecturally-visible bits of the machine to indicate that the first logical processor is allowed to operate in the relaxed memory access synchronization mode,
wherein, when allowed to operate in the relaxed memory access synchronization mode, the first logical processor is to prevent a memory access synchronization instruction from synchronizing accesses to a memory.

Assignees

• Intel Corp

Inventors

• Dixon Martin G
• Rash William C
• Santiago Yazmin A

Classifications

• G06F12/0804 Primary

  with main memory updating (G06F12/0806 takes precedence) · CPC title

• G06F2212/6028

  Prefetching based on hints or prefetch instructions · CPC title

• G06F12/0815

  Cache consistency protocols · CPC title

• G06F12/14 Primary

  Protection against unauthorised use of memory {or access to memory} · CPC title

• G06F12/0862

  with prefetch · CPC title