Bypassing a store-conditional request around a store queue

Patent metadata

Field	Value
Publication number	US-9304936-B2
Application number	US-201314100356-A
Country	US
Kind code	B2
Filing date	Dec 9, 2013
Priority date	Dec 9, 2013
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

In response to receipt of a store-conditional (STCX) request of a processor core, the STCX request is buffered in an entry of a store queue for eventual service by a read-claim (RC) machine by reference to a cache array, and the STCX request is concurrently transmitted via a bypass path bypassing the store queue. In response to dispatch logic dispatching the STCX request transmitted via the bypass path to the RC machine for service by reference to the cache array, the entry of the STCX request in the store queue is updated to prohibit selection of the STCX request in the store queue for service. In response to the STCX request transmitted via the bypass path not being dispatched by the dispatch logic, the STCX is thereafter transmitted from the store queue to the dispatch logic and dispatched to the RC machine for service by reference to the cache array.

First claim

What is claimed is:

1. A data processing system comprising:
a processor core;
a cache array,
a read-claim (RC) machine that services requests of the processor core by reference to the cache array;
dispatch logic that dispatches requests of the processor core to the RC machine for service;
a store queue coupled between the processor core and dispatch logic, the store queue including a plurality of entries for buffering requests of the processor core;
a bypass path coupling the processor core and dispatch logic that bypasses the store queue, wherein a store-conditional (STCX) request of the processor core is buffered in an entry of the store queue for eventual service by the RC machine by reference to the cache array and concurrently transmitted via the bypass path; and
a store queue controller that, in response to the dispatch logic dispatching the STCX request transmitted via the bypass path to the RC machine for service by reference to the cache array, updates the entry of the STCX request in the store queue to prohibit selection of the STCX request in the store queue for service, and, in response to the STCX request transmitted via the bypass path not being dispatched by the dispatch logic, causes the STCX to be transmitted from the store queue to the dispatch logic for service.

2. The data processing system of claim 1 , and further comprising:
selection logic that receives as inputs the STCX request transmitted via the bypass path, a selected request from among a plurality of requests buffered in the store queue, and a load request received from the processor core and selects, from among the requests received as inputs, a request to be processed by the dispatch logic, wherein the selection logic preferentially selects STCX requests transmitted via the bypass path.

3. The data processing system of claim 2 , wherein the store queue controller selects the selected request among the plurality of requests and presents the selected request to the selection logic for possible selection for processing by the dispatch logic.

4. The data processing system of claim 2 , wherein:
the STCX request transmitted via the bypass path is not dispatched in response to the selection logic selecting another request other than the STCX request transmitted via the bypass path for processing by the dispatch logic.

5. The data processing system of claim 1 , wherein the store queue controller, in response to the dispatch logic dispatching the STCX request transmitted via the bypass path to the RC machine for service by reference to the cache array, updates the entry of the STCX request in the store queue by invalidating the entry.

6. The data processing system of claim 1 , wherein:
the store queue controller, in response to the STCX request transmitted via the bypass path not being dispatched by the dispatch logic, updates the entry of the STCX request in the store queue to make the STCX request in the store queue eligible for selection for processing by the dispatch logic; and
the store queue controller causes the STCX request to be transmitted from the store queue only after the update to the entry of the STCX request in the store queue to make the STCX request in the store queue eligible for selection for processing by the dispatch logic.

7. The data processing system of claim 1 , wherein the processor core, cache array, read-claim (RC) machine, dispatch logic, store queue, a bypass path and store queue controller are implemented in a single first integrated circuit.

8. The data processing system of claim 7 , and further comprising:
a second integrated circuit;
a system fabric coupling the first and second integrated circuits; and
a system memory coupled to the system fabric.

9. A design structure tangibly embodied in a machine-readable storage device for designing, manufacturing, or testing an integrated circuit, the design structure comprising:
a data processing system, including:
a processor core;
a cache array,
a read-claim (RC) machine that services requests of the processor core by reference to the cache array;
dispatch logic that dispatches requests of the processor core to the RC machine for service;
a store queue coupled between the processor core and dispatch logic, the store queue including a plurality of entries for buffering requests of the processor core;
a bypass path coupling the processor core and dispatch logic that bypasses the store queue, wherein a store-conditional (STCX) request of the processor core is buffered in an entry of the store queue for eventual service by the RC machine by reference to the cache array and concurrently transmitted via the bypass path; and
a store queue controller that, in response to the dispatch logic dispatching the STCX request transmitted via the bypass path to the RC machine for service by reference to the cache array, updates the entry of the STCX request in the store queue to prohibit selection of the STCX request in the store queue for service, and, in response to the STCX request transmitted via the bypass path not being dispatched by the dispatch logic, causes the STCX to be transmitted from the store queue to the dispatch logic for service.

10. The design structure of claim 9 , and further comprising:
selection logic that receives as inputs the STCX request transmitted via the bypass path, a selected request from among a plurality of requests buffered in the store queue, and a load request received from the processor core and selects, from among the requests received as inputs, a request to be processed by the dispatch logic, wherein the selection logic preferentially selects STCX requests transmitted via the bypass path.

11. The design structure of claim 10 , wherein the store queue controller selects the selected request among the plurality of requests and presents the selected request to the selection logic for possible selection for processing by the dispatch logic.

12. The design structure of claim 10 , wherein:
the STCX request transmitted via the bypass path is not dispatched in response to the selection logic selecting another request other than the STCX request transmitted via the bypass path for processing by the dispatch logic.

13. The design structure of claim 9 , wherein the store queue controller, in response to the dispatch logic dispatching the STCX request transmitted via the bypass path to the RC machine for service by reference to the cache array, updates the entry of the STCX request in the store queue by invalidating the entry.

14. The design structure of claim 9 , wherein:
the store queue controller, in response to the STCX request transmitted via the bypass path not being dispatched by the dispatch logic, updates the entry of the STCX request in the store queue to make the STCX request in the store queue eligible for selection for processing by the dispatch logic; and
the store queue controller causes the STCX request to be transmitted from the store queue only after the update to the entry of the STCX request in the store queue to make the STCX request in the store queue eligible for selection for processing by the dispatch logic.

Assignees

• IBM

Inventors

• Ghai Sanjeev
• Guthrie Guy L
• Shen Hugh
• Williams Derek E

Classifications

• G06F12/0888 Primary

  using selective caching, e.g. bypass · CPC title

• G06F12/0895

  of parts of caches, e.g. directory or tag array · CPC title

• G06F9/3834

  Maintaining memory consistency · CPC title

• G06F12/0811

  with multilevel cache hierarchies · CPC title

• G06F9/3004

  to perform operations on memory · CPC title