Methodology for testing integrated circuits

Patent metadata

Field	Value
Publication number	US-9304163-B2
Application number	US-201314074672-A
Country	US
Kind code	B2
Filing date	Nov 7, 2013
Priority date	Nov 7, 2013
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

An integrated circuit is disclosed. The integrated circuit includes input and output pads, a first integrated circuit portion having first circuitry, and a second integrated circuit portion having second circuitry different from the first circuitry. The first integrated circuit portion is configured to provide an input test signal from the input pad to the second integrated circuit portion, and provide an output test signal from the second integrated circuit portion to the output pad, the output test signal being generated by second integrated circuit portion in response to the input test signal.

First claim

What is claimed is:

1. An integrated circuit, comprising:
input and output pads;
a first integrated circuit portion having first circuitry, wherein the first integrated circuit portion comprises a processor and a memory; and
a second integrated circuit portion having second circuitry different from the first circuitry, wherein the second integrated circuit portion comprises a transmitter and a digital-to-analog converter, or a receiver and an analog-to-digital converter;
wherein the first integrated circuit portion is configured to:
provide an input test signal from the input pad to the second integrated circuit portion,
wherein the input test signal comprises a mode signal that signals the second integrated circuit portion to be in a test mode,
wherein each of the first and second integrated circuit portions comprises one or more die-to-die pads, and the first and second integrated circuit portions are electrically connected together through their respective one or more die pads,
wherein the mode signal is provided to the second integrated circuit portion via the one or more die pads, and
wherein the processor and the memory are coupled to the at least one or more die pads, and the transmitter and the digital-to-analog converter or the receiver and the analog-to-digital converter are coupled to the one or more die pads; and

provide an output test signal from the second integrated circuit portion to the output pad, the output test signal being generated by the second integrated circuit portion in response to the input test signal.

2. The integrated circuit of claim 1 , wherein the first and second integrated circuit portions are fabricated on different wafers.

3. The integrated circuit of claim 1 , wherein the first integrated circuit portion comprises a baseband processor and the second integrated circuit portion comprises a modem configured to modulate a carrier signal with data generated by the baseband processor and to demodulate a carrier signal to recover data transmitted from a remote apparatus.

4. The integrated circuit of claim 1 , further comprising one or more general purpose input/output (GPIO) pads comprising the input and output pads.

5. The integrated circuit of claim 1 , wherein the first and second integrated circuit portions are configured to enter a test mode, and wherein the first integrated circuit portion provides the input test signal from the input pad to the second integrated circuit portion in response to entering the test mode, and wherein the first integrated circuit portion provides the output test signal from the second integrated circuit portion to the output pad in response to entering the test mode.

6. The integrated circuit of claim 5 , wherein the test mode comprises a scan test mode.

7. The integrated circuit of claim 5 , wherein the test mode comprises a functional test mode.

8. The integrated circuit of claim 5 , wherein the first integrated circuit portion is further configured to cause the second integrated circuit portion to enter the test mode in response to one or more control signals from the input pad.

9. The integrated circuit of claim 6 , wherein the first integrated circuit portion is further configured to cause the second integrated circuit portion to enter the test mode by providing one or more control signals to the second integrated circuit portion.

10. The integrated circuit of claim 5 , wherein the first integrated circuit portion comprises a multiplexer configured to provide the input test signal from the input pad to the second integrated circuit portion, and a demultiplexer configured to provide the output test signal to the output pad.

11. The integrated circuit of claim 1 , wherein the first integrated circuit portion comprises an input pass-through for the input test signal from the input pad to the second integrated circuit portion, and an output pass-through circuit further for the output test signal from the second integrated circuit portion to the output pad.

12. A method of testing an integrated circuit having input and output pads, a first integrated circuit portion having first circuitry, and a second integrated circuit portion having second circuitry different from the first circuitry, the method comprising:
providing an input test signal from the input pad through the first integrated circuit portion to the second integrated circuit portion, wherein the first integrated circuit portion comprises a processor and a memory, and the second integrated circuit portion comprises a transmitter and a digital-to-analog converter, or a receiver and an analog-to-digital converter,
wherein the input test signal comprises a mode signal that signals the second integrated circuit portion to be in a test mode,
wherein each of the first and second integrated circuit portions comprises one or more die-to-die pads, and the first and second integrated circuit portions are electrically connected together through their respective one or more die pads,
wherein the mode signal is provided to the second integrated circuit portion via the one or more die pads, and
wherein the processor and the memory are coupled to the at least one or more die pads, and the transmitter and the digital-to-analog converter or the receiver and the analog-to-digital converter are coupled to the one or more die pads;

generating an output test signal in response to the input test signal at the second integrated circuit portion; and
providing the output test signal from the second integrated circuit portion through the first integrated circuit portion to the output pad.

13. The method of claim 12 , wherein the first and second integrated circuit portions are fabricated on different wafers.

14. The method of claim 12 , wherein the first integrated circuit portion comprises a baseband processor and the second integrated circuit portion comprises a modem configured to modulate a carrier signal with data generated by the baseband processor and to demodulate a carrier signal to recover data transmitted from a remote apparatus.

15. The method of claim 12 , wherein the integrated circuit further comprises one or more general purpose input/output (GPIO) pads comprising the input and output pads.

16. The method of claim 12 , further comprising causing the first and second integrated circuit portions to enter a test mode, wherein the input test signal is provided by the first integrated circuit portion from the input pad to the second integrated circuit portion in response to entering the test mode, and wherein the output test signal is provided by the first integrated circuit portion from the second integrated circuit portion to the output pad in response to entering the test mode.

17. The method of claim 16 , wherein the entering the test mode comprises performing a scan test.

18. The method of claim 16 , wherein the entering the test mode comprises a performing a functional test.

19. The method of claim 16 , wherein the first integrated circuit portion causes the second integrated circuit portion to enter the test mode in response to one or more control signals from the input pad.

20. The method of claim 16 , wherein the first integrated circuit portion causes the second integrated circuit portion to enter the test mode by providing one or more control signals to the second integrated circuit portion.

21. The method of claim 12 , wherein the providing the input test signal from the input pad to the second integrated circuit portion comprises passing input test signal through

Assignees

• Qualcomm Inc

Inventors

• Bhogela Sagar
• Cynthia Daisy
• Srinivasan Srikanth

Classifications

• G01R31/2894

  Aspects of quality control [QC] (G01R31/31718 takes precedence; program control for QC G05B19/41875) · CPC title

• G01R31/2896 Primary

  Testing of IC packages; Test features related to IC packages (containers per se H10W76/10, encapsulations per se H10W74/00) · CPC title

• G01R31/318558

  Addressing or selecting of subparts of the device under test · CPC title

• G01R31/318513 Primary

  Test of Multi-Chip-Moduls · CPC title

• G01R31/2884

  using dedicated test connectors, test elements or test circuits on the IC under test (G01R31/2855 takes precedence) · CPC title