Printed circuit board with burr prevention structure

Patent metadata

Field	Value
Publication number	US-9301387-B2
Application number	US-201313774655-A
Country	US
Kind code	B2
Filing date	Feb 22, 2013
Priority date	Mar 2, 2012
Publication date	Mar 29, 2016
Grant date	Mar 29, 2016

Abstract

A PCB according to an exemplary embodiment of the present disclosure includes a plurality of unit PCBs arrayed on the PCB, and a sawing line formed among the plurality of unit PCBs. The sawing line disposed among the dummy unit PCBs is formed with a conductive pad including a first layer formed with a PSR (Photo Solder Resistor) and a second layer on which the PSR is removed to open the conductive pad. Burr generation on the unit PCBs during a sawing process is prevented and a dummy area can be reduced.

First claim

What is claimed is:

1. A PCB with burr prevention structure, the PCB comprising:
a plurality of unit PCBs arrayed on the PCB;
a plurality of dummy PCBs arranged at a periphery of the unit PCBs;
a first sawing line formed among the plurality of unit PCBs; and
a second sawing line formed among the plurality of dummy PCBs and connected to the first sawing line,
wherein the second sawing line is formed with an ID (identification) mark for a sawing process of the PCB,
wherein the ID mark includes a conductive pad comprising a first laver formed with a Photo Solder Resistor (PSR) and a second laver on which the PSR is removed at a predetermined area to open the conductive pad, and
wherein the first sawing line is formed at each corner of the plurality of unit PCBs with a hole to inhibit the corner of the unit PCBs from being sharpened;
wherein the first sawing line includes grooves formed at an upper surface and a bottom surface of the PCB.

2. The PCB of claim 1 , wherein each of the first sawing line and the second sawing line is formed with a groove.

3. The PCB of claim 1 , wherein each of the unit PCBs is a single layer PCB or a multilayer (build-up) PCB.

4. The PCB of claim 1 , wherein a width of each of the first sawing line and the second sawing line is less than 300 μm.

5. The PCB of claim 2 , wherein each groove is connected with the first sawing line and the second sawing line.

6. The PCB of claim 2 , wherein each groove is a V-shaped groove.

Assignees

• Lg Innotek Co Ltd

Inventors

• Ryou Chung Sang

Classifications

• H05K3/0008

  for aligning or positioning of tools relative to the circuit board (H05K3/4638, H05K3/4679 take precedence; for manufacturing assemblages of components H05K13/0015) · CPC title

• H05K2201/0909

  Preformed cutting or breaking line · CPC title

• H05K2201/09918

  Optically detected marks used for aligning tool relative to the PCB, e.g. for mounting of components · CPC title

• H05K2201/09063

  Holes or slots in insulating substrate not used for electrical connections · CPC title

• H05K3/0052 Primary

  Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards · CPC title