Voltage doubling circuit for an analog to digital converter (ADC)

Patent metadata

Field	Value
Publication number	US-9300316-B2
Application number	US-201514616464-A
Country	US
Kind code	B2
Filing date	Feb 6, 2015
Priority date	Feb 28, 2014
Publication date	Mar 29, 2016
Grant date	Mar 29, 2016

Abstract

In one embodiment, a circuit includes a first input of a comparator for an analog to digital converter (ADC). The first input is coupled to a first capacitive network. The circuit further includes a second input of the comparator for the ADC. The second input is coupled to a second capacitive network. The first capacitive network includes a first set of capacitors where a first plate of the first set of capacitors is selectively coupled to an input signal. The second capacitive network includes a second set of capacitors where a second plate of the first set of capacitors is selectively coupled to the input signal. The first plate and the second plate are opposite plates of the first set of capacitors and the second set of capacitors.

First claim

What is claimed is:

1. A circuit comprising:
a first input of a comparator for an analog to digital converter (ADC), the first input being coupled to a first capacitive network; and
a second input of the comparator for the ADC, the second input being coupled to a second capacitive network,
wherein:
the first capacitive network includes a first set of capacitors, wherein a first plate of the first set of capacitors is selectively coupled to a single-ended input signal and a second plate of the first set of capacitors is selectively coupled to a direct current (DC) reference bias of the single-ended input signal,
the second capacitive network includes a second set of capacitors, wherein a second plate of the second set of capacitors is selectively coupled to the single-ended input signal and a first plate of the second set of capacitors is selectively coupled to the DC reference bias of the single-ended input signal, and
the first plate of the first set of capacitors and the first plate of the second set of capacitors are opposite plates from the second plate of the first set of capacitors and the second plate of the second set of capacitors.

2. The circuit of claim 1 , wherein a voltage swing of the input signal is doubled at the first input and the second input of the comparator using the first capacitive network and the second capacitive network.

3. The circuit of claim 1 , wherein:
a first reference voltage and a second reference voltage are selectively coupled to the first plate of the first set of capacitors, and
the first reference voltage and the second reference voltage are selectively coupled to the first plate of the second set of capacitors.

4. The circuit of claim 3 , wherein:
the first plate of the first set of capacitors and the second set of capacitors is a bottom plate, and
the second plate of the first set of capacitors and the second set of capacitors is a top plate.

5. The circuit of claim 1 , wherein a common mode of the comparator is constant during a decision making process of converting the input signal to a digital value.

6. The circuit of claim 5 , wherein the common mode of the comparator is based on a first reference voltage and a second reference voltage selectively coupled to the first set of capacitors and the second set of capacitors.

7. The circuit of claim 1 , further comprising:
a controller coupled to the comparator, wherein the controller is configured to selectively couple a first reference voltage and a second reference voltage to the first set of capacitors and the second set of capacitors.

8. The circuit of claim 7 , wherein:
the controller selectively couples the first reference voltage and the second reference voltage to the first plate of the first set of capacitors, and
the controller selectively couples the first reference voltage and the second reference voltage to a first plate of the second set of capacitors.

9. A method comprising:
coupling a first input of a comparator for an analog to digital converter (ADC to a first capacitive network;
coupling a second input of the comparator for the ADC to a second capacitive network;
selectively coupling an input signal to a first plate for a first set of capacitors in the first capacitive network and selectively coupling a second plate of the first set of capacitors to a direct current (DC) reference bias of the single-ended input signal; and
selectively coupling the input signal to a second plate for a second set of capacitors in the second capacitive network and selectively coupling a first plate of the second set of capacitors to the DC reference bias of the single-ended input signal,
the first plate of the first set of capacitors and the first plate of the second set of capacitors are opposite plates from the second plate of the first set of capacitors and the second plate of the second set of capacitors.

10. The method of claim 9 , wherein a voltage swing of the input signal is doubled at the first input and the second input of the comparator using the first capacitive network and the second capacitive network.

11. The method of claim 9 , further comprising:
selectively coupling a first reference voltage and a second reference voltage to the first plate of the first set of capacitors, and
selectively coupling the first reference voltage and the second reference voltage to the first plate of the second set of capacitors.

12. The method of claim 11 wherein:
the first plate of the first set of capacitors and the second set of capacitors is a bottom plate, and
the second plate of the first set of capacitors and the second set of capacitors is a top plate.

13. The method of claim 9 , wherein a common mode of the comparator is constant during a decision making process of converting the input signal to a digital value.

14. An analog to digital converter (ADC) comprising:
a digital to analog converter (DAC) comprising a first capacitive network including a first set of capacitors and a second capacitive network including a second set of capacitors; and
a comparator comprising:
a first input of a comparator, the first input being coupled to the first capacitive network; and
a second input of the comparator, the second input being coupled to the second capacitive network,
wherein:
a first plate of the first set of capacitors is selectively coupled to a single-ended input signal and a second plate of the first set of capacitors is selectively coupled to a direct current (DC) reference bias of the single-ended input signal,
a second plate of the second set of capacitors is selectively coupled to the single-ended input signal and a first plate of the second set of capacitors is selectively coupled to the DC reference bias of the single-ended input signal, and
the first plate of the first set of capacitors and the first plate of the second set of capacitors are opposite plates from the seond plate of the first set of capacitors and the second plate of the second set of capacitors.

15. The method of claim 13 , wherein the common mode of the comparator is based on a first reference voltage and a second reference voltage selectively coupled to the first set of capacitors and the second set of capacitors.

16. The method of claim 9 , further comprising:
coupling a controller to the comparator, wherein the controller is configured to selectively couple a first reference voltage and a second reference voltage to the first set of capacitors and the second set of capacitors.

17. The method of claim 16 , wherein:
the controller selectively couples the first reference voltage and the second reference voltage to the first plate of the first set of capacitors, and
the controller selectively couples the first reference voltage and the second reference voltage to a first plate of the second set of capacitors.

18. The ADC of claim 14 , wherein a voltage swing of the input signal is doubled at the first input and the second input of the comparator using the first capacitive network and the second capacitive network.

19. The ADC of claim 14 , wherein:
a first reference voltage and a second reference voltage are selectively coupled to the first plate of the first set of capacitors, and
the first reference voltage and the second reference voltage are selectively coupled to the first plate of the second set of capacitors.

20. The ADC of claim 19 , wherein:
the first plate of the first set of capacitors and the second set of capacitors is a bottom plate, and
the second plate of the first set of capacito

Assignees

• Qualcomm Inc

Inventors

• Alladi Dinesh Jagannath
• Baker Sean
• Sivakumar Balasubramanian
• Huang Wei
• Yuan Dan

Classifications

• H03M1/468

  in which the input S/H circuit is merged with the feedback DAC array · CPC title

• H03M1/38

  sequentially only, e.g. successive approximation type (converting more than one bit per step H03M1/14) · CPC title

• H03M1/1245 Primary

  Details of sampling arrangements or methods · CPC title

• H03M1/0682 Primary

  using a differential network structure, i.e. symmetrical with respect to ground · CPC title

• H03M1/403

  using switched capacitors · CPC title