Semiconductor devices including a dummy gate structure on a fin

Patent metadata

Field	Value
Publication number	US-9299700-B2
Application number	US-201514639494-A
Country	US
Kind code	B2
Filing date	Mar 5, 2015
Priority date	May 8, 2014
Publication date	Mar 29, 2016
Grant date	Mar 29, 2016

Abstract

Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.

First claim

What is claimed is:

1. A semiconductor device comprising:
a fin protruding from a substrate and extending in a direction;
a recess in the fin;
a device isolation layer filling the recess;
a dummy gate structure overlapping the device isolation layer;
first and second spacers at opposite sides of the dummy gate structure on the fin;
an inner spacer on inner sidewalls of the first and second spacers; and
a source/drain region at opposite sides of the recess and spaced apart from the device isolation layer.

2. The semiconductor device of claim 1 , wherein a first width of the recess is narrower than a second width of the dummy gate structure.

3. The semiconductor device of claim 2 , wherein a first bottom surface of the recess is lower than a second bottom surface of the source/drain region.

4. The semiconductor device of claim 1 , wherein:
the first spacer comprises a first region and a second region on the first region;
the second spacer comprises a third region and a fourth region on the third region;
a first width of the first region is wider than a second width of the second region; and
a third width of the third region is wider than a fourth width of the fourth region.

5. The semiconductor device of claim 4 , wherein a first distance between the first region and the third region is shorter than a second distance between the second region and the fourth region.

6. The semiconductor device of claim 1 , further comprising a capping layer between the recess and the device isolation layer and continuously extending adjacent a boundary of the recess.

7. The semiconductor device of claim 1 , further comprising a cover layer on a top surface of the dummy gate structure.

8. The semiconductor device of claim 7 , wherein the first and second spacers extend along respective sidewalls of the cover layer.

9. The semiconductor device of claim 1 , wherein a top surface of the device isolation layer protrudes beyond or is coplanar with a top surface of the fin.

10. The semiconductor device of claim 9 ,
wherein the device isolation layer comprises a first region in the recess and a second region on the first region, and
wherein a first width of the first region is narrower than a second width of the second region.

11. The semiconductor device of claim 1 , further comprising a first gate structure and a second gate structure spaced apart from the dummy gate structure at opposite sides, respectively, of the dummy gate structure on the fin.

12. The semiconductor device of claim 11 , wherein a bottom surface of the dummy gate structure is higher than or coplanar with respective bottom surfaces of the first and second gate structures.

13. A semiconductor device comprising:
a fin protruding from a substrate and extending in a direction;
a recess in the fin;
a dummy gate structure filling the recess;
first and second gate structures at opposite sides of the dummy gate structure, respectively, wherein the first and second gate structures are spaced apart from the dummy gate structure on the fin and extend over the fin;
a first spacer on the first gate structure, a second spacer on the second gate structure, and a third spacer comprising respective portions on the opposite sides of the dummy gate structure; and
an inner spacer between the dummy gate structure and the third spacer.

14. The semiconductor device of claim 13 , wherein a first width of the recess is narrower than a second width of the dummy gate structure on the recess.

15. The semiconductor device of claim 13 ,
wherein the dummy gate structure comprises a gate insulation layer, a barrier layer and a gate electrode, and
wherein the gate electrode is in the recess.

16. A semiconductor device comprising:
a fin protruding from a substrate;
a source/drain region in the fin;
a device isolation layer in a recess region of the fin that is between and spaced apart from first and second portions of the source/drain region;
a dummy gate structure overlapping the device isolation layer; and
a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.

17. The semiconductor device of claim 16 , further comprising first and second gate structures on the fin, wherein the dummy gate structure is between the first and second gate structures.

18. The semiconductor device of claim 17 , further comprising a protective cover layer on the dummy gate structure and the first and second gate structures.

19. The semiconductor device of claim 16 ,
wherein the spacer comprises a first spacer, and
wherein the semiconductor device further comprises a second spacer that is on a sidewall of the first spacer and that undercuts a portion of the dummy gate structure.

20. The semiconductor device of claim 16 , wherein the device isolation layer is tapered away from the dummy gate structure.

Assignees

• Park Sang-Jine
• Kwon Kee-Sang
• Kim Do-Hyoung
• Yoon Bo-Un
• Bai Keun-Hee
• Yang Kwang-Yong
• Yeo Kyoung-Hwan
• Jeon Yong-Ho
• Samsung Electronics Co Ltd

Inventors

• Park Sang-Jine
• Kwon Kee-Sang
• Kim Do-Hyoung
• Yoon Bo-Un
• Bai Keun-Hee
• Yang Kwang-Yong
• Yeo Kyoung-Hwan
• Jeon Yong-Ho

Classifications

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D30/797

  being in source or drain regions, e.g. SiGe source or drain · CPC title

• H10D30/611

  having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733) · CPC title

• H10D30/62 Primary

  Fin field-effect transistors [FinFET] · CPC title