Physically unclonable function based on breakdown voltage of metal-insulator-metal device

Patent metadata

Field	Value
Publication number	US-9298946-B2
Application number	US-201314072735-A
Country	US
Kind code	B2
Filing date	Nov 5, 2013
Priority date	Sep 9, 2013
Publication date	Mar 29, 2016
Grant date	Mar 29, 2016

Abstract

One feature pertains to a method of implementing a physically unclonable function that includes providing an array of metal-insulator-metal (MIM) devices, where the MIM devices are configured to represent a first resistance state or a second resistance state and a plurality of the MIM devices are initially at the first resistance state. The MIM devices have a random breakdown voltage that is greater than a first voltage and less than a second voltage, where the breakdown voltage represents a voltage that causes the MIM devices to transition from the first resistance state to the second resistance state. The method further includes applying a signal line voltage to the MIM devices to cause a portion of the MIM devices to randomly breakdown and transition from the first resistance state to the second resistance state, the signal line voltage greater than the first voltage and less than the second voltage.

First claim

What is claimed is:

1. A method of implementing a physically unclonable function (PUF), the method comprising:
providing an array of metal-insulator-metal (MIM) devices each having a tunnel junction layer, the MIM devices each configured to represent one of a first resistance logical state or a second resistance logical state and at least a plurality of the MIM devices are initially at the first resistance logical state, each of the MIM devices having a random breakdown voltage V BR that is greater than a first voltage V 1 and less than a second voltage V 2 , the breakdown voltage V BR representing a voltage level that causes the tunnel junction layer of a respective MIM device to breakdown and transition the respective MIM device from the first resistance logical state to the second resistance logical state, the first resistance logical state having a greater resistance than the second resistance logical state, and wherein the breakdown voltage V BR of any particular MIM device within the array depends on random manufacturing variations in doping concentrations; and
applying a signal line voltage V SL to each of the MIM devices to cause the tunnel junction layers within at least a portion of the plurality of MIM devices to randomly breakdown based on the random manufacturing variations in doping concentrations and transition from the first resistance logical state to the second resistance logical state, the signal line voltage V SL , greater than the first voltage V 1 and less than the second voltage V 2 .

2. The method of claim 1 , further comprising:
sending a challenge to the array of MIM devices that reads logical states of select MIM devices of the array; and
obtaining a response to the challenge from the array of MIM devices that includes the logical states of the selected MIM devices of the array.

3. The method of claim 2 , wherein the array of MIM devices is an array of magnetoresistive random access memory (MRAM) circuit cells.

4. The method of claim 3 , wherein the challenge includes MRAM device address information, and the response includes data bit information of MRAM devices corresponding to the MRAM device address information.

5. The method of claim 3 , wherein the MRAM circuit cells lack an anti-ferromagnetic (AFM) pinning layer.

6. The method of claim 5 , wherein the MRAM circuit cells have a reference layer that includes a single ferromagnetic layer.

7. The method of claim 1 , wherein the signal line voltage V SL , is about equal to a voltage level V 3 that corresponds to a voltage level that causes about half of the MIM devices in the array to breakdown and change logical state from the first resistance logical state to the second resistance logical state.

8. The method of claim 1 , wherein the logical states of the MIM devices of the array after the signal line voltage V SL is applied are stored in secure memory.

9. The method of claim 1 , wherein the logical states of the MIM devices of the array after the signal line voltage V SL is applied serve as a cryptographic key that uniquely identifies an electronic device.

10. The method of claim 1 , wherein the logical states of the MIM devices of the array after the signal line voltage V SL , is applied are utilized by a cryptographic security algorithm.

11. The method of claim 1 , wherein applying a signal line voltage V SL to each of the MIM devices to cause the tunnel junction layers within at least a portion of the plurality of MIM devices to randomly breakdown is performed to cause the tunnel junction layers to breakdown due to other variations on an atomic level in addition to the variations in doping concentrations.

12. The method of claim 1 , wherein each tunnel junction layer is flat and excludes any macroscopic deformations.

13. The method of claim 1 , wherein the breakdown voltage of any particular MIM device within the array depends on random manufacturing variations in the tunnel junction layer of the particular MIM device that are distinct from manufacturing variations in other layers of the MIM and wherein the signal line voltage is applied to cause the tunnel junction layers to randomly breakdown based on the random manufacturing variations in the tunnel junction layers that are distinct from manufacturing variations in other layers of the MIM.

14. The method of claim 1 , wherein the breakdown voltage of any particular MIM device within the array depends on random manufacturing variations in the tunnel junction layer of the particular MIM device that are not caused by manufacturing variations in other layers of the MIM and wherein the signal line voltage is applied to cause the tunnel junction layers to randomly breakdown based on the random manufacturing variations in the tunnel junction layers that are not caused by manufacturing variations in other layers of the MIM.

15. An apparatus for implementing a physically unclonable function (PUF), the apparatus comprising:
an array of metal-insulator-metal (MIM) devices each having a tunnel junction layer and each configured to represent one of a first resistance logical state or a second resistance logical state and at least a plurality of the MIM devices are initially at the first resistance logical state, each of the MIM devices having a random breakdown voltage V BR that is greater than a first voltage V 1 and less than a second voltage V 2 , the breakdown voltage V BR representing a voltage level that causes the tunnel junction layer of a respective MIM device to breakdown and transition the respective MIM device from the first resistance logical state to the second resistance logical state, the first resistance logical state having a greater resistance than the second resistance logical state, and wherein the breakdown voltage V BR of any particular MIM device within the array depends on random manufacturing variations in doping concentrations; and
a processing circuit communicatively coupled to the MIM devices and configured to apply a signal line voltage V SL to each of the MIM devices to cause the tunnel junction layers within at least a portion of the plurality of MIM devices to randomly breakdown based on the random manufacturing variations in doping concentrations and transition from the first resistance logical state to the second resistance logical state, the signal line voltage V SL greater than the first voltage V 1 and less than the second voltage V 2 .

16. The apparatus of claim 15 , wherein the processing circuit is further configured to:
send a challenge to the array of MIM devices that reads logical states of select MIM devices of the array; and
obtain a response to the challenge from the array of MIM devices that includes the logical states of the selected MIM devices of the array.

17. The apparatus of claim 16 , wherein the array of MIM devices is an array of magnetoresistive random access memory (MRAM) circuit cells.

18. The apparatus of claim 17 , wherein the challenge includes MRAM device address information, and the response includes data bit information of MRAM devices corresponding to the MRAM device address information.

19. The apparatus of claim 17 , wherein the MRAM circuit cells lack an anti-ferromagnetic (AFM) pinning layer.

20. The apparatus of claim 19 , wherein the MRAM circuit cells have a reference layer that includes a single ferromagnetic layer.

21. The apparatus of claim 15 , wherein the signal line voltage V SL is about equal to a voltage level V 3 that corresponds to a voltage level that causes about half of the MIM devices

Assignees

• Qualcomm Inc

Inventors

• Zhu Xiaochun
• Millendorf Steven M
• Guo Xu
• Jacobson David M
• Lee Kangho
• Kang Seung H
• Nowak Matthew Michael

Classifications

• G11C11/161 Primary

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• H04L2209/12

  Details relating to cryptographic hardware or logic circuitry · CPC title

• G11C17/02

  using magnetic or inductive elements (G11C17/14 takes precedence) · CPC title

• H04L9/0866

  involving user or device identifiers, e.g. serial number, physical or biometrical information, DNA, hand-signature or measurable physical characteristics · CPC title

• G11C11/1675

  Writing or programming circuits or methods · CPC title